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Searched refs:opc1 (Results 1 – 25 of 25) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td4143 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4151 bits<3> opc1;
4158 let Inst{23-21} = opc1;
4168 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4176 bits<4> opc1;
4182 let Inst{7-4} = opc1;
4191 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4193 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4196 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4197 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
[all …]
DARMInstrInfo.td4314 class SMLAL<bits<2> opc1, string asm>
4315 : AMulxyI64<0b0001010, opc1,
5078 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5080 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
5081 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
5084 bits<4> opc1;
5097 let Inst{23-20} = opc1;
5102 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
5104 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
5105 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td4151 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4159 bits<3> opc1;
4166 let Inst{23-21} = opc1;
4174 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
4182 bits<4> opc1;
4188 let Inst{7-4} = opc1;
4195 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
4197 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4200 def : t2InstAlias<"mcr${p} $cop, $opc1, $Rt, $CRn, $CRm",
4201 (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
[all …]
DARMInstrInfo.td4812 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4814 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4815 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4818 bits<4> opc1;
4831 let Inst{23-20} = opc1;
4834 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4836 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4837 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4841 bits<4> opc1;
4854 let Inst{23-20} = opc1;
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrInfo.td4214 def CDP : ABI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4216 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4217 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4219 bits<4> opc1;
4232 let Inst{23-20} = opc1;
4235 def CDP2 : ABXI<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4237 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4238 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4241 bits<4> opc1;
4254 let Inst{23-20} = opc1;
[all …]
DARMInstrThumb2.td3620 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3628 bits<3> opc1;
3635 let Inst{23-21} = opc1;
3644 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
3645 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
3653 bits<4> opc1;
3659 let Inst{7-4} = opc1;
3666 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
3668 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
3671 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
[all …]
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.td221 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
222 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
230 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
231 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
237 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
239 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
258 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,
260 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
269 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,
271 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/
DXCoreInstrInfo.td214 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
215 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
223 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
224 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
230 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
232 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
251 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,
253 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
262 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,
264 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
Dnv50_ir_emit_gk110.cpp48 void emitForm_21(const Instruction *, uint32_t opc2, uint32_t opc1);
422 uint32_t opc1) in emitForm_21() argument
432 code[1] = opc1 << 20; in emitForm_21()
1844 uint64_t opc1, opc2; in emitSUCalc() local
1853 case OP_SUCLAMP: opc1 = 0xb00; opc2 = 0x580; break; in emitSUCalc()
1854 case OP_SUBFM: opc1 = 0xb68; opc2 = 0x1e8; break; in emitSUCalc()
1855 case OP_SUEAU: opc1 = 0xb6c; opc2 = 0x1ec; break; in emitSUCalc()
1860 emitForm_21(i, opc2, opc1); in emitSUCalc()
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td5116 class T_shift_imm_acc_r <string opc1, string opc2, SDNode OpNode1,
5120 "$Rx "#opc2#opc1#"($Rs, #$u5)",
5146 class T_shift_reg_acc_r <string opc1, string opc2, SDNode OpNode1,
5150 "$Rx "#opc2#opc1#"($Rs, $Rt)",
5173 class T_shift_imm_acc_p <string opc1, string opc2, SDNode OpNode1,
5177 "$Rxx "#opc2#opc1#"($Rss, #$u6)",
5203 class T_shift_reg_acc_p <string opc1, string opc2, SDNode OpNode1,
5207 "$Rxx "#opc2#opc1#"($Rss, $Rt)",
5238 multiclass xtype_imm_acc<string opc1, SDNode OpNode, bits<2>minOp> {
5240 defm _acc : xtype_imm_base< opc1, "+= ", OpNode, add, 0b001, minOp>;
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrControl.td52 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
53 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, []>;
/external/llvm/lib/Target/X86/
DX86InstrControl.td85 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
86 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm,
DX86InstrAVX512.td2411 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2413 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
2416 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode>,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrControl.td75 multiclass ICBr<bits<8> opc1, bits<8> opc4, string asm, PatFrag Cond> {
76 def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm,
DX86InstrAVX512.td3109 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
3111 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode,
3114 defm B : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "b"), VK8, OpNode,
/external/v8/src/arm/
Ddisasm-arm.cc1671 int opc1 = instr->Bits(23, 21); in DecodeTypeCP15() local
1673 if ((opc1 == 0) && (crn == 7)) { in DecodeTypeCP15()
Dsimulator-arm.cc3526 int opc1 = instr->Bits(23, 21); in DecodeTypeCP15() local
3528 if ((opc1 == 0) && (crn == 7)) { in DecodeTypeCP15()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenGlobalISel.inc20350 …2] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (imm:{ *:[i32] }):$CRm) => (MCRR…
20353 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // opc1
20390 …] }):$opc1, GPRnopc:{ *:[i32] }:$Rt, GPRnopc:{ *:[i32] }:$Rt2, (imm:{ *:[i32] }):$CRm) => (MCRR2…
20393 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // opc1
20428 …[i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (imm:{ *:[i32] }):$CRm) => (t2MCRR (i…
20431 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // opc1
20468 …i32] }):$opc1, GPR:{ *:[i32] }:$Rt, GPR:{ *:[i32] }:$Rt2, (imm:{ *:[i32] }):$CRm) => (t2MCRR2 (i…
20471 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // opc1
20526 …opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$o…
20529 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/2, // opc1
[all …]
DARMGenMCCodeEmitter.inc4332 // op: opc1
4518 // op: opc1
4651 // op: opc1
4668 // op: opc1
8406 // op: opc1
10343 // op: opc1
10546 // op: opc1
10703 // op: opc1
10779 // op: opc1
10797 // op: opc1
DARMGenDAGISel.inc10021 /* 21339*/ OPC_RecordChild3, // #2 = $opc1
10054 …trinsic_void 969:{ *:[iPTR] }, (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):…
10055 …// Dst: (CDP (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i3…
10069 …trinsic_void 969:{ *:[iPTR] }, (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):…
10070 …// Dst: (t2CDP (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[…
10078 /* 21451*/ OPC_RecordChild3, // #2 = $opc1
10109 …trinsic_void 970:{ *:[iPTR] }, (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):…
10110 …// Dst: (CDP2 (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i…
10124 …trinsic_void 970:{ *:[iPTR] }, (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):…
10125 …// Dst: (t2CDP2 (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:…
[all …]
/external/capstone/arch/ARM/
DARMGenAsmWriter.inc8878 // (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p)
8889 // (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0)
8933 // (MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p)
8944 // (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0)
10906 // (t2MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p)
10917 // (t2MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p)
10937 // (t2MRC GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p)
10948 // (t2MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm, 0, pred:$p)
DARMDisassembler.c5096 unsigned opc1 = fieldFromInstruction_4(Val, 4, 4); in DecodeMRRC2() local
5108 MCOperand_CreateImm0(Inst, opc1); in DecodeMRRC2()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp5297 unsigned opc1 = fieldFromInstruction(Val, 4, 4); in DecoderForMRRC2AndMCRR2() local
5325 Inst.addOperand(MCOperand::createImm(opc1)); in DecoderForMRRC2AndMCRR2()
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp5274 unsigned opc1 = fieldFromInstruction(Val, 4, 4); in DecoderForMRRC2AndMCRR2() local
5302 Inst.addOperand(MCOperand::createImm(opc1)); in DecoderForMRRC2AndMCRR2()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td9867 bit opc1, bit opc2, RegisterOperand dst_reg,
9893 let Inst{15} = opc1;
9905 multiclass SIMDIndexedTiedComplexHSD<bit U, bit opc1, bit opc2, Operand rottype,
9908 def v4f16_indexed : BaseSIMDIndexedTiedComplex<0, 1, 0, 0b01, opc1, opc2, V64,
9916 def v8f16_indexed : BaseSIMDIndexedTiedComplex<1, 1, 0, 0b01, opc1, opc2,
9926 def v4f32_indexed : BaseSIMDIndexedTiedComplex<1, 1, 0, 0b10, opc1, opc2,