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Searched refs:opc2 (Results 1 – 25 of 28) sorted by relevance

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/external/llvm/test/TableGen/
DBitsInit.td7 bits<2> opc2 = { 1, 0 };
9 bits<2> a = { opc, opc2 }; // error!
10 bits<2> b = { opc{0}, opc2{0} };
11 bits<2> c = { opc{1}, opc2{1} };
17 // CHECK: bits<2> opc2 = { 1, 0 };
/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
DBitsInit.td7 bits<2> opc2 = { 1, 0 };
9 bits<2> a = { opc, opc2 }; // error!
10 bits<2> b = { opc{0}, opc2{0} };
11 bits<2> c = { opc{1}, opc2{1} };
17 // CHECK: bits<2> opc2 = { 1, 0 };
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.td221 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
225 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
230 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
233 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
237 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
242 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
258 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,
263 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
269 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,
274 def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/
DXCoreInstrInfo.td214 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
218 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
223 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
226 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
230 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
235 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
251 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,
256 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
262 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,
267 def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
Dnv50_ir_emit_gk110.cpp48 void emitForm_21(const Instruction *, uint32_t opc2, uint32_t opc1);
421 CodeEmitterGK110::emitForm_21(const Instruction *i, uint32_t opc2, in emitForm_21() argument
435 code[1] = (0xc << 28) | (opc2 << 20); in emitForm_21()
1844 uint64_t opc1, opc2; in emitSUCalc() local
1853 case OP_SUCLAMP: opc1 = 0xb00; opc2 = 0x580; break; in emitSUCalc()
1854 case OP_SUBFM: opc1 = 0xb68; opc2 = 0x1e8; break; in emitSUCalc()
1855 case OP_SUEAU: opc1 = 0xb6c; opc2 = 0x1ec; break; in emitSUCalc()
1860 emitForm_21(i, opc2, opc1); in emitSUCalc()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrThumb2.td3620 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
3629 bits<3> opc2;
3636 let Inst{7-5} = opc2;
3667 c_imm:$CRm, imm0_7:$opc2),
3669 imm:$CRm, imm:$opc2)]>;
3672 c_imm:$CRm, imm0_7:$opc2),
3674 imm:$CRm, imm:$opc2)]>;
3679 c_imm:$CRm, imm0_7:$opc2), []>;
3683 c_imm:$CRm, imm0_7:$opc2), []>;
3685 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
[all …]
DARMInstrInfo.td4215 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4216 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4218 imm:$CRm, imm:$opc2)]> {
4223 bits<3> opc2;
4228 let Inst{7-5} = opc2;
4236 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4237 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4239 imm:$CRm, imm:$opc2)]> {
4245 bits<3> opc2;
4250 let Inst{7-5} = opc2;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrThumb2.td4143 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4152 bits<3> opc2;
4159 let Inst{7-5} = opc2;
4192 c_imm:$CRm, imm0_7:$opc2),
4194 imm:$CRm, imm:$opc2)]>,
4201 c_imm:$CRm, imm0_7:$opc2),
4203 imm:$CRm, imm:$opc2)]> {
4213 c_imm:$CRm, imm0_7:$opc2), []>;
4220 c_imm:$CRm, imm0_7:$opc2), []> {
4227 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
[all …]
DARMInstrInfo.td5079 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
5080 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
5082 imm:$CRm, imm:$opc2)]>,
5088 bits<3> opc2;
5093 let Inst{7-5} = opc2;
5103 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
5104 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
5106 imm:$CRm, imm:$opc2)]>,
5113 bits<3> opc2;
5118 let Inst{7-5} = opc2;
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrThumb2.td4151 : T2Cop<Op, oops, iops, opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2",
4160 bits<3> opc2;
4167 let Inst{7-5} = opc2;
4196 c_imm:$CRm, imm0_7:$opc2),
4198 imm:$CRm, imm:$opc2)]>,
4205 c_imm:$CRm, imm0_7:$opc2),
4207 imm:$CRm, imm:$opc2)]> {
4217 c_imm:$CRm, imm0_7:$opc2), []>;
4224 c_imm:$CRm, imm0_7:$opc2), []> {
4231 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
[all …]
DARMInstrInfo.td4813 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4814 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4816 imm:$CRm, imm:$opc2)]>,
4822 bits<3> opc2;
4827 let Inst{7-5} = opc2;
4835 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
4836 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
4838 imm:$CRm, imm:$opc2)]>,
4845 bits<3> opc2;
4850 let Inst{7-5} = opc2;
[all …]
/external/v8/src/arm/
Ddisasm-arm.cc1672 int opc2 = instr->Bits(7, 5); in DecodeTypeCP15() local
1676 if ((crm == 10) && (opc2 == 5)) { in DecodeTypeCP15()
1678 } else if ((crm == 10) && (opc2 == 4)) { in DecodeTypeCP15()
1680 } else if ((crm == 5) && (opc2 == 4)) { in DecodeTypeCP15()
Dsimulator-arm.cc3527 int opc2 = instr->Bits(7, 5); in DecodeTypeCP15() local
3531 if (((crm == 10) && (opc2 == 5)) || // CP15DMB in DecodeTypeCP15()
3532 ((crm == 10) && (opc2 == 4)) || // CP15DSB in DecodeTypeCP15()
3533 ((crm == 5) && (opc2 == 4))) { // CP15ISB in DecodeTypeCP15()
Dassembler-arm.cc3063 int sz, opc2, op; in EncodeVCVT() local
3066 opc2 = IsSignedVFPType(dst_type) ? 0x5 : 0x4; in EncodeVCVT()
3071 opc2 = 0x0; in EncodeVCVT()
3076 return (cond | 0xE*B24 | B23 | D*B22 | 0x3*B20 | B19 | opc2*B16 | in EncodeVCVT()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrMMX.td41 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
53 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrMMX.td53 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
68 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
DX86InstrSSE.td3435 multiclass PDI_binop_rmi<bits<8> opc, bits<8> opc2, Format ImmForm,
3458 def ri : PDIi8<opc2, ImmForm, (outs RC:$dst),
3467 multiclass PDI_binop_rmi_all<bits<8> opc, bits<8> opc2, Format ImmForm,
3474 defm V#NAME : PDI_binop_rmi<opc, opc2, ImmForm, !strconcat("v", OpcodeStr),
3478 defm V#NAME#Y : PDI_binop_rmi<opc, opc2, ImmForm, !strconcat("v", OpcodeStr),
3483 defm NAME : PDI_binop_rmi<opc, opc2, ImmForm, OpcodeStr, OpNode, OpNode2,
/external/llvm/lib/Target/X86/
DX86InstrMMX.td113 multiclass MMXI_binop_rmi_int<bits<8> opc, bits<8> opc2, Format ImmForm,
127 def ri : MMXIi8<opc2, ImmForm, (outs VR64:$dst),
DX86InstrAVX512.td2411 multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
2419 defm Q : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "q"), VK64, OpNode>,
2421 defm D : avx512_mask_shiftop<opc2, !strconcat(OpcodeStr, "d"), VK32, OpNode>,
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td5116 class T_shift_imm_acc_r <string opc1, string opc2, SDNode OpNode1,
5120 "$Rx "#opc2#opc1#"($Rs, #$u5)",
5146 class T_shift_reg_acc_r <string opc1, string opc2, SDNode OpNode1,
5150 "$Rx "#opc2#opc1#"($Rs, $Rt)",
5173 class T_shift_imm_acc_p <string opc1, string opc2, SDNode OpNode1,
5177 "$Rxx "#opc2#opc1#"($Rss, #$u6)",
5203 class T_shift_reg_acc_p <string opc1, string opc2, SDNode OpNode1,
5207 "$Rxx "#opc2#opc1#"($Rss, $Rt)",
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenGlobalISel.inc20526 …opc2) => (CDP (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *:…
20533 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/6, // opc2
20581 …opc2) => (CDP2 (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ *…
20588 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/6, // opc2
20634 …opc2) => (t2CDP (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRd, (imm:{ …
20641 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/6, // opc2
20689 …opc2) => (t2CDP2 (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$CRd, (imm:{…
20696 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/6, // opc2
20740 …:$opc2) => (MRC:{ *:[i32] } (imm:{ *:[i32] }):$cop, (imm:{ *:[i32] }):$opc1, (imm:{ *:[i32] }):$…
20747 GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/5, // opc2
[all …]
DARMGenDAGISel.inc10037 /* 21363*/ OPC_RecordChild7, // #6 = $opc2
10054 …}):$CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2) - Complexity = 26
10055 …1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)
10069 …}):$CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2) - Complexity = 26
10070 …1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)
10094 /* 21475*/ OPC_RecordChild7, // #6 = $opc2
10109 …}):$CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2) - Complexity = 26
10110 …1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)
10124 …}):$CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2) - Complexity = 26
10125 …1, (imm:{ *:[i32] }):$CRd, (imm:{ *:[i32] }):$CRn, (imm:{ *:[i32] }):$CRm, (imm:{ *:[i32] }):$opc2)
[all …]
DARMGenMCCodeEmitter.inc4521 // op: opc2
4671 // op: opc2
8418 // op: opc2
10706 // op: opc2
10782 // op: opc2
10809 // op: opc2
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td9867 bit opc1, bit opc2, RegisterOperand dst_reg,
9895 let Inst{12} = opc2;
9905 multiclass SIMDIndexedTiedComplexHSD<bit U, bit opc1, bit opc2, Operand rottype,
9908 def v4f16_indexed : BaseSIMDIndexedTiedComplex<0, 1, 0, 0b01, opc1, opc2, V64,
9916 def v8f16_indexed : BaseSIMDIndexedTiedComplex<1, 1, 0, 0b01, opc1, opc2,
9926 def v4f32_indexed : BaseSIMDIndexedTiedComplex<1, 1, 0, 0b10, opc1, opc2,
DSVEInstrFormats.td1460 class sve_int_read_vl_a<bit op, bits<5> opc2, string asm>
1470 let Inst{20-16} = opc2{4-0};

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