/external/v8/src/interpreter/ |
D | bytecode-node.h | 30 V8_INLINE BytecodeNode(Bytecode bytecode, uint32_t operand0, 37 SetOperand(0, operand0); in bytecode_() 40 V8_INLINE BytecodeNode(Bytecode bytecode, uint32_t operand0, 48 SetOperand(0, operand0); in bytecode_() 52 V8_INLINE BytecodeNode(Bytecode bytecode, uint32_t operand0, 60 SetOperand(0, operand0); in bytecode_() 65 V8_INLINE BytecodeNode(Bytecode bytecode, uint32_t operand0, 74 SetOperand(0, operand0); in bytecode_() 80 V8_INLINE BytecodeNode(Bytecode bytecode, uint32_t operand0, 89 SetOperand(0, operand0); in bytecode_() [all …]
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D | bytecode-array-builder.cc | 167 uint32_t operand0 = static_cast<uint32_t>(src.ToOperand()); in OutputMovRaw() local 170 BytecodeNode::Mov(BytecodeSourceInfo(), operand0, operand1)); in OutputMovRaw()
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/external/mesa3d/src/gallium/drivers/svga/ |
D | svga_tgsi_vgpu10.c | 745 VGPU10OperandToken0 operand0, in setup_operand0_indexing() argument 755 if (operand0.operandType == VGPU10_OPERAND_TYPE_IMMEDIATE32 || in setup_operand0_indexing() 756 operand0.operandType == VGPU10_OPERAND_TYPE_INPUT_PRIMITIVEID) { in setup_operand0_indexing() 759 assert(operand0.selectionMode == 0); in setup_operand0_indexing() 764 operand0.operandType == VGPU10_OPERAND_TYPE_CONSTANT_BUFFER) { in setup_operand0_indexing() 804 operand0.indexDimension = indexDim; in setup_operand0_indexing() 805 operand0.index0Representation = index0Rep; in setup_operand0_indexing() 806 operand0.index1Representation = index1Rep; in setup_operand0_indexing() 808 return operand0; in setup_operand0_indexing() 822 VGPU10OperandToken0 operand0; in emit_indirect_register() local [all …]
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/external/tensorflow/tensorflow/compiler/xla/service/gpu/ |
D | fusion_merger_test.cc | 89 auto* operand0 = root->operand(0); in TEST_F() local 90 EXPECT_EQ(HloOpcode::kFusion, operand0->opcode()); in TEST_F() 91 EXPECT_EQ(4, operand0->fused_instruction_count()); in TEST_F()
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/external/v8/src/compiler/ia32/ |
D | instruction-selector-ia32.cc | 203 InstructionOperand operand0 = g.UseRegister(node->InputAt(0)); in VisitRROFloat() local 206 selector->Emit(avx_opcode, g.DefineAsRegister(node), operand0, operand1); in VisitRROFloat() 208 selector->Emit(sse_opcode, g.DefineSameAsFirst(node), operand0, operand1); in VisitRROFloat() 226 InstructionOperand operand0 = g.UseRegister(node->InputAt(0)); in VisitRRSimd() local 228 selector->Emit(avx_opcode, g.DefineAsRegister(node), operand0); in VisitRRSimd() 230 selector->Emit(sse_opcode, g.DefineSameAsFirst(node), operand0); in VisitRRSimd() 237 InstructionOperand operand0 = g.UseRegister(node->InputAt(0)); in VisitRRISimd() local 240 selector->Emit(opcode, g.DefineAsRegister(node), operand0, operand1); in VisitRRISimd() 246 InstructionOperand operand0 = g.UseRegister(node->InputAt(0)); in VisitRRISimd() local 250 selector->Emit(avx_opcode, g.DefineAsRegister(node), operand0, operand1); in VisitRRISimd() [all …]
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/external/v8/src/compiler/x64/ |
D | instruction-selector-x64.cc | 1244 InstructionOperand operand0 = g.UseRegister(node->InputAt(0)); in VisitFloatBinop() local 1247 selector->Emit(avx_opcode, g.DefineAsRegister(node), operand0, operand1); in VisitFloatBinop() 1249 selector->Emit(sse_opcode, g.DefineSameAsFirst(node), operand0, operand1); in VisitFloatBinop()
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/external/tensorflow/tensorflow/compiler/xla/service/ |
D | hlo_evaluator_test.cc | 117 auto operand0 = in TestTernaryOp() local 124 expected.shape(), opcode, operand0, operand1, operand2)); in TestTernaryOp()
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/external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
D | AMDGPUUsage.rst | 4095 *<opcode> <operand0>, <operand1>,... <modifier0> <modifier1>...*
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/external/toolchain-utils/dejagnu/gdb_baseline/ |
D | x86_64-cros-linux-gnu | 16569 PASS: gdb.opt/clobbered-registers-O2.exp: print operand0
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D | i686-pc-linux-gnu | 16301 PASS: gdb.opt/clobbered-registers-O2.exp: print operand0
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D | armv7a-cros-linux-gnueabi | 16199 PASS: gdb.opt/clobbered-registers-O2.exp: print operand0
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