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Searched refs:orn (Results 1 – 25 of 131) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/SVE/
Dorn-diagnostics.s6 orn z5.b, z5.b, #0xfa label
11 orn z5.b, z5.b, #0xfff9 label
16 orn z5.h, z5.h, #0xfffa label
21 orn z5.h, z5.h, #0xfffffff9 label
26 orn z5.s, z5.s, #0xfffffffa label
31 orn z5.s, z5.s, #0xffffffffffffff9 label
36 orn z15.d, z15.d, #0xfffffffffffffffa label
44 orn z7.d, z8.d, #254 label
49 orn z7.d, z8.d, #254 label
58 orn p0.h, p0/z, p0.h, p1.h label
[all …]
Dorn.s10 orn z5.b, z5.b, #0xf9 label
16 orn z23.h, z23.h, #0xfff9 label
22 orn z0.s, z0.s, #0xfffffff9 label
28 orn z0.d, z0.d, #0xfffffffffffffff9 label
34 orn z5.b, z5.b, #0x6 label
40 orn z23.h, z23.h, #0x6 label
46 orn z0.s, z0.s, #0x6 label
52 orn z0.d, z0.d, #0x6 label
58 orn p0.b, p0/z, p0.b, p0.b label
64 orn p15.b, p15/z, p15.b, p15.b label
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/
Dthumb2-orn.ll10 ; CHECK: orn r0, r0, r1
18 ; CHECK: orn r0, r0, r1
26 ; CHECK: orn r0, r0, r1
34 ; CHECK: orn r0, r0, r1
43 ; CHECK: orn r0, r0, r1, lsl #5
52 ; CHECK: orn r0, r0, r1, lsr #6
61 ; CHECK: orn r0, r0, r1, asr #7
72 ; CHECK: orn r0, r0, r0, ror #8
Dthumb2-orn2.ll11 ; CHECK: orn r0, r0, #187
20 ; CHECK: orn r0, r0, #11141290
29 ; CHECK: orn r0, r0, #-872363008
38 ; CHECK: orn r0, r0, #1114112
/external/llvm/test/CodeGen/Thumb2/
Dthumb2-orn.ll9 ; CHECK: orn r0, r0, r1
17 ; CHECK: orn r0, r0, r1
25 ; CHECK: orn r0, r0, r1
33 ; CHECK: orn r0, r0, r1
42 ; CHECK: orn r0, r0, r1, lsl #5
51 ; CHECK: orn r0, r0, r1, lsr #6
60 ; CHECK: orn r0, r0, r1, asr #7
71 ; CHECK: orn r0, r0, r0, ror #8
Dthumb2-orn2.ll10 ; CHECK: orn r0, r0, #187
19 ; CHECK: orn r0, r0, #11141290
28 ; CHECK: orn r0, r0, #-872363008
37 ; CHECK: orn r0, r0, #1114112
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb2/
Dthumb2-orn.ll9 ; CHECK: orn r0, r0, r1
17 ; CHECK: orn r0, r0, r1
25 ; CHECK: orn r0, r0, r1
33 ; CHECK: orn r0, r0, r1
42 ; CHECK: orn r0, r0, r1, lsl #5
51 ; CHECK: orn r0, r0, r1, lsr #6
60 ; CHECK: orn r0, r0, r1, asr #7
71 ; CHECK: orn r0, r0, r0, ror #8
Dthumb2-orn2.ll10 ; CHECK: orn r0, r0, #187
19 ; CHECK: orn r0, r0, #11141290
28 ; CHECK: orn r0, r0, #-872363008
37 ; CHECK: orn r0, r0, #1114112
/external/llvm/test/MC/AArch64/
Darm64-logical-encoding.s204 orn w1, w2, w3
205 orn x1, x2, x3
206 orn w1, w2, w3, lsl #7
207 orn x1, x2, x3, lsl #7
208 orn w1, w2, w3, lsr #7
209 orn x1, x2, x3, lsr #7
210 orn w1, w2, w3, asr #7
211 orn x1, x2, x3, asr #7
212 orn w1, w2, w3, ror #7
213 orn x1, x2, x3, ror #7
[all …]
Dalias-logicalimm.s26 orn x0, x1, #2
31 orn w2, w1, #3
Dneon-bitwise-instructions.s45 orn v0.8b, v1.8b, v2.8b
46 orn v0.16b, v1.16b, v2.16b
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Darm64-logical-encoding.s204 orn w1, w2, w3
205 orn x1, x2, x3
206 orn w1, w2, w3, lsl #7
207 orn x1, x2, x3, lsl #7
208 orn w1, w2, w3, lsr #7
209 orn x1, x2, x3, lsr #7
210 orn w1, w2, w3, asr #7
211 orn x1, x2, x3, asr #7
212 orn w1, w2, w3, ror #7
213 orn x1, x2, x3, ror #7
[all …]
Dalias-logicalimm.s32 orn x0, x1, #2
38 orn w2, w1, #3
Dneon-bitwise-instructions.s45 orn v0.8b, v1.8b, v2.8b
46 orn v0.16b, v1.16b, v2.16b
/external/llvm/test/MC/Disassembler/AArch64/
Darm64-logical.txt214 # CHECK: orn w1, w2, w3
215 # CHECK: orn x1, x2, x3
216 # CHECK: orn w1, w2, w3, lsl #7
217 # CHECK: orn x1, x2, x3, lsl #7
218 # CHECK: orn w1, w2, w3, lsr #7
219 # CHECK: orn x1, x2, x3, lsr #7
220 # CHECK: orn w1, w2, w3, asr #7
221 # CHECK: orn x1, x2, x3, asr #7
222 # CHECK: orn w1, w2, w3, ror #7
223 # CHECK: orn x1, x2, x3, ror #7
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/
Darm64-logical.txt214 # CHECK: orn w1, w2, w3
215 # CHECK: orn x1, x2, x3
216 # CHECK: orn w1, w2, w3, lsl #7
217 # CHECK: orn x1, x2, x3, lsl #7
218 # CHECK: orn w1, w2, w3, lsr #7
219 # CHECK: orn x1, x2, x3, lsr #7
220 # CHECK: orn w1, w2, w3, asr #7
221 # CHECK: orn x1, x2, x3, asr #7
222 # CHECK: orn w1, w2, w3, ror #7
223 # CHECK: orn x1, x2, x3, ror #7
/external/llvm/test/CodeGen/Hexagon/intrinsics/
Dcr.ll102 declare i32 @llvm.hexagon.C4.and.orn(i32, i32, i32)
104 %z = call i32@llvm.hexagon.C4.and.orn(i32 %a, i32 %b, i32 %c)
123 declare i32 @llvm.hexagon.C2.orn(i32, i32)
125 %z = call i32@llvm.hexagon.C2.orn(i32 %a, i32 %b)
130 declare i32 @llvm.hexagon.C4.or.orn(i32, i32, i32)
132 %z = call i32@llvm.hexagon.C4.or.orn(i32 %a, i32 %b, i32 %c)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/intrinsics/
Dcr.ll102 declare i32 @llvm.hexagon.C4.and.orn(i32, i32, i32)
104 %z = call i32@llvm.hexagon.C4.and.orn(i32 %a, i32 %b, i32 %c)
123 declare i32 @llvm.hexagon.C2.orn(i32, i32)
125 %z = call i32@llvm.hexagon.C2.orn(i32 %a, i32 %b)
130 declare i32 @llvm.hexagon.C4.or.orn(i32, i32, i32)
132 %z = call i32@llvm.hexagon.C4.or.orn(i32 %a, i32 %b, i32 %c)
/external/llvm/test/CodeGen/AArch64/
Dlogical_shifted_reg.ll14 ; First check basic and/bic/or/orn/eor/eon patterns with no shift
28 ; CHECK: orn {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
53 ; CHECK: orn {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
78 ; CHECK: orn {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #1
104 ; First check basic and/bic/or/orn/eor/eon patterns with no shift
118 ; CHECK: orn {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
143 ; CHECK: orn {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63
168 ; CHECK: orn {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #1
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Dlogical_shifted_reg.ll14 ; First check basic and/bic/or/orn/eor/eon patterns with no shift
28 ; CHECK: orn {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
53 ; CHECK: orn {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsl #31
78 ; CHECK: orn {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, lsr #1
104 ; First check basic and/bic/or/orn/eor/eon patterns with no shift
118 ; CHECK: orn {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
143 ; CHECK: orn {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsl #63
168 ; CHECK: orn {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, lsr #1
/external/capstone/suite/MC/AArch64/
Dneon-bitwise-instructions.s.cs14 0x20,0x1c,0xe2,0x0e = orn v0.8b, v1.8b, v2.8b
15 0x20,0x1c,0xe2,0x4e = orn v0.16b, v1.16b, v2.16b
/external/swiftshader/third_party/llvm-7.0/llvm/test/Linker/Inputs/
Dthumb-module-inline-asm.ll3 module asm "orn r1, r2, r2"
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Sparc/
Dsparc-alu-instructions.s31 ! CHECK: orn %g1, %g2, %g3 ! encoding: [0x86,0x30,0x40,0x02]
32 orn %g1, %g2, %g3
/external/llvm/test/MC/Sparc/
Dsparc-alu-instructions.s31 ! CHECK: orn %g1, %g2, %g3 ! encoding: [0x86,0x30,0x40,0x02]
32 orn %g1, %g2, %g3
/external/swiftshader/third_party/llvm-7.0/llvm/test/Linker/
Dlink-arm-and-thumb-module-inline-asm.ll20 ; CHECK-NEXT: orn r1, r2, r2

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