| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/SVE/ |
| D | orns-diagnostics.s | 6 orns p0.h, p0/z, p0.h, p1.h label
11 orns p0.s, p0/z, p0.s, p1.s label
16 orns p0.d, p0/z, p0.d, p1.d label
24 orns p0.b, p0/m, p1.b, p2.b label
|
| D | orns.s | 10 orns p0.b, p0/z, p0.b, p0.b label
16 orns p15.b, p15/z, p15.b, p15.b label
|
| /external/capstone/suite/MC/ARM/ |
| D | basic-thumb2-instructions.s.cs | 535 0x75,0xea,0x06,0x04 = orns r4, r5, r6
537 0x75,0xea,0x56,0x14 = orns r4, r5, r6, lsr #5
539 0x75,0xea,0x66,0x14 = orns r4, r5, r6, asr #5
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 1279 orns r4, r5, r6
1281 orns r4, r5, r6, lsr #5
1283 orns r4, r5, r6, asr #5
1288 @ CHECK: orns r4, r5, r6 @ encoding: [0x75,0xea,0x06,0x04]
1290 @ CHECK: orns r4, r5, r6, lsr #5 @ encoding: [0x75,0xea,0x56,0x14]
1292 @ CHECK: orns r4, r5, r6, asr #5 @ encoding: [0x75,0xea,0x66,0x14]
|
| /external/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 1680 orns r4, r5, r6
1682 orns r4, r5, r6, lsr #5
1684 orns r4, r5, r6, asr #5
1689 @ CHECK: orns r4, r5, r6 @ encoding: [0x75,0xea,0x06,0x04]
1691 @ CHECK: orns r4, r5, r6, lsr #5 @ encoding: [0x75,0xea,0x56,0x14]
1693 @ CHECK: orns r4, r5, r6, asr #5 @ encoding: [0x75,0xea,0x66,0x14]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 1728 orns r4, r5, r6
1730 orns r4, r5, r6, lsr #5
1732 orns r4, r5, r6, asr #5
1737 @ CHECK: orns r4, r5, r6 @ encoding: [0x75,0xea,0x06,0x04]
1739 @ CHECK: orns r4, r5, r6, lsr #5 @ encoding: [0x75,0xea,0x56,0x14]
1741 @ CHECK: orns r4, r5, r6, asr #5 @ encoding: [0x75,0xea,0x66,0x14]
|
| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-operand-const-t32.cc | 63 M(orns) \
|
| D | test-assembler-cond-rd-rn-operand-rm-t32.cc | 63 M(orns) \
|
| D | test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 63 M(orns) \
|
| D | test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 63 M(orns) \
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 1104 # CHECK: orns r4, r5, r6
1106 # CHECK: orns r4, r5, r6, lsr #5
1108 # CHECK: orns r4, r5, r6, asr #5
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 1221 # CHECK: orns r4, r5, r6
1223 # CHECK: orns r4, r5, r6, lsr #5
1225 # CHECK: orns r4, r5, r6, asr #5
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 1221 # CHECK: orns r4, r5, r6
1223 # CHECK: orns r4, r5, r6, lsr #5
1225 # CHECK: orns r4, r5, r6, asr #5
|
| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.cc | 1060 orns(cond, rd, rn, ~imm); in Delegate()
|
| D | assembler-aarch32.h | 2724 void orns(Condition cond, Register rd, Register rn, const Operand& operand);
2725 void orns(Register rd, Register rn, const Operand& operand) { in orns() function
2726 orns(al, rd, rn, operand); in orns()
|
| D | disasm-aarch32.h | 952 void orns(Condition cond, Register rd, Register rn, const Operand& operand);
|
| D | disasm-aarch32.cc | 2012 void Disassembler::orns(Condition cond, in orns() function in vixl::aarch32::Disassembler
8636 orns(CurrentCond(), Register(rd), Register(rn), imm); in DecodeT32()
19200 orns(CurrentCond(), in DecodeT32()
19223 orns(CurrentCond(), in DecodeT32()
|
| D | assembler-aarch32.cc | 7737 void Assembler::orns(Condition cond, in orns() function in vixl::aarch32::Assembler
7776 Delegate(kOrns, &Assembler::orns, cond, rd, rn, operand); in orns()
|
| D | macro-assembler-aarch32.h | 2745 orns(cond, rd, rn, operand); in Orns()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SVEInstrInfo.td | 262 def ORNS_PPzPP : sve_int_pred_log<0b1101, "orns">;
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 11886 "ngcs\003nop\003nor\004nors\003not\004nots\003orn\004orns\003orr\004orrs"
15834 …{ 3190 /* orns */, AArch64::ORNS_PPzPP, Convert__SVEPredicateBReg1_0__SVEPredicateAnyReg1_1__SVEPr…
22303 …{ 3190 /* orns */, AArch64::ORNS_PPzPP, Convert__SVEPredicateBReg1_0__SVEPredicateAnyReg1_1__SVEPr…
32125 { Feature_HasSVE, 3190 /* orns */, MCK_SVEPredicateBReg, 49 /* 0, 4, 5 */ },
32126 { Feature_HasSVE, 3190 /* orns */, MCK_SVEPredicateAnyReg, 2 /* 1 */ },
32127 { Feature_HasSVE, 3190 /* orns */, MCK_SVEPredicateBReg, 49 /* 0, 4, 5 */ },
32128 { Feature_HasSVE, 3190 /* orns */, MCK_SVEPredicateAnyReg, 2 /* 1 */ },
|