/external/mesa3d/src/amd/addrlib/r800/ |
D | egbaddrlib.cpp | 102 ADDR_TILEINFO* pTileInfo = &tileInfoDef; in DispatchComputeSurfaceInfo() local 123 ADDR_ASSERT(pOut->pTileInfo); in DispatchComputeSurfaceInfo() 125 if (pOut->pTileInfo != NULL) in DispatchComputeSurfaceInfo() 127 pTileInfo = pOut->pTileInfo; in DispatchComputeSurfaceInfo() 131 if (pIn->pTileInfo != NULL) in DispatchComputeSurfaceInfo() 133 if (pTileInfo != pIn->pTileInfo) in DispatchComputeSurfaceInfo() 135 *pTileInfo = *pIn->pTileInfo; in DispatchComputeSurfaceInfo() 140 memset(pTileInfo, 0, sizeof(ADDR_TILEINFO)); in DispatchComputeSurfaceInfo() 150 pIn->pTileInfo, in DispatchComputeSurfaceInfo() 151 pTileInfo, in DispatchComputeSurfaceInfo() [all …]
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D | egbaddrlib.h | 111 UINT_32 bankSwizzle, UINT_32 pipeSwizzle, ADDR_TILEINFO* pTileInfo, 126 BOOL_32 isTcCompatible, BOOL_32 isLinear, ADDR_TILEINFO* pTileInfo) const; 186 ADDR_TILEINFO* pTileInfo) const = 0; 195 UINT_32 tileX, UINT_32 bank, ADDR_TILEINFO* pTileInfo) const = 0; 202 ADDR_TILEINFO* pTileInfo) const = 0; 231 virtual UINT_32 HwlStereoCheckRightOffsetPadding(ADDR_TILEINFO* pTileInfo) const; 236 ADDR_TILEINFO* pTileInfo) const; 245 ADDR_TILEINFO* pTileInfo) const; 249 UINT_32 base256b, ADDR_TILEINFO* pTileInfo, 254 UINT_64 baseAddr, ADDR_TILEINFO* pTileInfo) const; [all …]
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D | siaddrlib.cpp | 142 const ADDR_TILEINFO* pTileInfo ///< [in] Tile info in HwlGetPipes() 147 if (pTileInfo) in HwlGetPipes() 149 numPipes = GetPipePerSurf(pTileInfo->pipeConfig); in HwlGetPipes() 221 ADDR_TILEINFO* pTileInfo, ///< [in] tile info in ComputeBankEquation() argument 227 UINT_32 pipes = HwlGetPipes(pTileInfo); in ComputeBankEquation() 228 UINT_32 bankXStart = 3 + Log2(pipes) + Log2(pTileInfo->bankWidth); in ComputeBankEquation() 229 UINT_32 bankYStart = 3 + Log2(pTileInfo->bankHeight); in ComputeBankEquation() 249 switch (pTileInfo->banks) in ComputeBankEquation() 252 if (pTileInfo->macroAspectRatio == 1) in ComputeBankEquation() 264 else if (pTileInfo->macroAspectRatio == 2) in ComputeBankEquation() [all …]
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D | ciaddrlib.cpp | 300 UINT_32 numOfPipes = HwlGetPipes(pIn->pTileInfo); in HwlComputeCmaskAddrFromCoord() 301 UINT_32 numOfBanks = pIn->pTileInfo->banks; in HwlComputeCmaskAddrFromCoord() 344 UINT_32 numOfPipes = HwlGetPipes(pIn->pTileInfo); in HwlComputeHtileAddrFromCoord() 345 UINT_32 numOfBanks = pIn->pTileInfo->banks; in HwlComputeHtileAddrFromCoord() 709 …pOut->tcCompatible = CheckTcCompatibility(pOut->pTileInfo, pIn->bpp, pOut->tileMode, pOut->tileTyp… in HwlComputeSurfaceInfo() 734 localIn.pTileInfo = NULL; in HwlComputeSurfaceInfo() 752 localIn.pTileInfo = NULL; in HwlComputeSurfaceInfo() 790 if (pOut->pTileInfo == NULL) in HwlComputeFmaskInfo() 792 pOut->pTileInfo = &tileInfo; in HwlComputeFmaskInfo() 829 macroModeIndex = HwlComputeMacroModeIndex(tileIndex, flags, bpp, numSamples, pOut->pTileInfo); in HwlComputeFmaskInfo() [all …]
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D | siaddrlib.h | 126 ADDR_TILEINFO* pTileInfo, UINT_32* pBitPosition) const; 131 ADDR_TILEINFO* pTileInfo, UINT_32* pX, UINT_32* pY, UINT_32* pSlice) const; 152 UINT_32 bpp, ADDR_TILEINFO* pTileInfo) const; 160 ADDR_TILEINFO* pTileInfo, ADDR_EQUATION* pEquation) const; 164 ADDR_TILEINFO* pTileInfo, ADDR_EQUATION* pEquation) const; 169 ADDR_TILEINFO* pTileInfo) const; 171 virtual UINT_32 HwlGetPipes(const ADDR_TILEINFO* pTileInfo) const; 218 ADDR_TILEINFO* pTileInfo) const in HwlSanityCheckMacroTiled() argument 235 ADDR_TILEINFO* pTileInfo) const; 238 UINT_32 tileX, UINT_32 bank, ADDR_TILEINFO* pTileInfo) const; [all …]
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D | ciaddrlib.h | 88 UINT_32 bpp, ADDR_TILEINFO* pTileInfo) const; 92 ADDR_TILEINFO* pTileInfo, AddrTileMode* pTileMode = NULL, AddrTileType* pTileType = NULL 144 UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 mipLevel, 180 BOOL_32 CheckTcCompatibility(const ADDR_TILEINFO* pTileInfo, UINT_32 bpp, AddrTileMode tileMode,
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/external/mesa3d/src/amd/addrlib/core/ |
D | addrlib1.cpp | 210 if (pIn->pTileInfo) in ComputeSurfaceInfo() 212 tileInfoNull = *pIn->pTileInfo; in ComputeSurfaceInfo() 214 localIn.pTileInfo = &tileInfoNull; in ComputeSurfaceInfo() 300 ADDR_ASSERT(localIn.pTileInfo); in ComputeSurfaceInfo() 313 localIn.pTileInfo, in ComputeSurfaceInfo() 323 localIn.pTileInfo, in ComputeSurfaceInfo() 470 input.pTileInfo = &tileInfoNull; in ComputeSurfaceAddrFromCoord() 480 input.pTileInfo, in ComputeSurfaceAddrFromCoord() 488 input.pTileInfo, &input.tileMode, &input.tileType); in ComputeSurfaceAddrFromCoord() 550 input.pTileInfo = &tileInfoNull; in ComputeSurfaceCoordFromAddr() [all …]
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D | addrlib1.h | 227 UINT_32 bankSwizzle, UINT_32 pipeSwizzle, ADDR_TILEINFO* pTileInfo, 237 BOOL_32 isTcCompatible, BOOL_32 isLinear, ADDR_TILEINFO* pTileInfo) const = 0; 319 ADDR_TILEINFO* pTileInfo, 328 ADDR_TILEINFO* pTileInfo, UINT_32* pPitchOut, UINT_32* pHeightOut, UINT_64* pCmaskBytes, 334 UINT_32 bpp, ADDR_TILEINFO* pTileInfo) const; 340 BOOL_32 isHeight8, ADDR_TILEINFO* pTileInfo, 346 ADDR_TILEINFO* pTileInfo, UINT_32* pX, UINT_32* pY, UINT_32* pSlice) const; 377 UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 padDims, UINT_32 mipLevel, 383 UINT_32 numSamples, ADDR_TILEINFO* pTileInfo, UINT_32 mipLevel, in HwlPadDimensions() argument 427 const ADDR_TILEINFO* pTileInfo) const; [all …]
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/external/mesa3d/src/amd/addrlib/ |
D | addrinterface.h | 566 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Set to 0 to default/calculate member 616 ADDR_TILEINFO* pTileInfo; ///< Tile parameters used. Filled in if 0 on input member 705 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data member 793 ADDR_TILEINFO* pTileInfo; ///< 2D tile parameters. Client must provide all data member 883 ADDR_TILEINFO* pTileInfo; ///< Tile info member 957 ADDR_TILEINFO* pTileInfo; ///< Tile info member 1020 ADDR_TILEINFO* pTileInfo; ///< Tile info member 1101 ADDR_TILEINFO* pTileInfo; ///< Tile info member 1172 ADDR_TILEINFO* pTileInfo; ///< Tile info member 1231 ADDR_TILEINFO* pTileInfo; ///< Tile info member [all …]
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/external/mesa3d/src/amd/common/ |
D | ac_surface.c | 340 AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo; in gfx6_compute_level() 368 AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo; in gfx6_compute_level() 427 surf->u.legacy.pipe_config = csio->pTileInfo->pipeConfig - 1; in gfx6_surface_settings() 432 surf->u.legacy.bankw = csio->pTileInfo->bankWidth; in gfx6_surface_settings() 433 surf->u.legacy.bankh = csio->pTileInfo->bankHeight; in gfx6_surface_settings() 434 surf->u.legacy.mtilea = csio->pTileInfo->macroAspectRatio; in gfx6_surface_settings() 435 surf->u.legacy.tile_split = csio->pTileInfo->tileSplitBytes; in gfx6_surface_settings() 436 surf->u.legacy.num_banks = csio->pTileInfo->banks; in gfx6_surface_settings() 458 AddrBaseSwizzleIn.pTileInfo = csio->pTileInfo; in gfx6_surface_settings() 503 AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut; in gfx6_compute_surface() [all …]
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