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Searched refs:pattern_table (Results 1 – 4 of 4) sorted by relevance

/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_training_bist.c30 struct pattern_info *pattern_table = ddr3_tip_get_pattern_table(); in ddr3_tip_bist_activate() local
47 pattern_table[pattern].tx_burst_size : 0; in ddr3_tip_bist_activate()
51 pattern_table[pattern].num_of_phases_tx, tx_burst_size, in ddr3_tip_bist_activate()
52 pattern_table[pattern].num_of_phases_rx, in ddr3_tip_bist_activate()
445 struct pattern_info *pattern_table = ddr3_tip_get_pattern_table(); in mv_ddr_odpg_bist_prepare() local
468 tx_burst_size = pattern_table[pattern].tx_burst_size; in mv_ddr_odpg_bist_prepare()
476 ddr3_tip_configure_odpg(0, access_type, 0, dir, pattern_table[pattern].num_of_phases_tx, in mv_ddr_odpg_bist_prepare()
477 tx_burst_size, pattern_table[pattern].num_of_phases_rx, burst_delay, in mv_ddr_odpg_bist_prepare()
488 struct pattern_info *pattern_table = ddr3_tip_get_pattern_table(); in mv_ddr_dm_vw_get() local
508 bist_offset, cs, pattern_table[pattern].num_of_phases_tx, in mv_ddr_dm_vw_get()
[all …]
Dddr3_training_ip_engine.c352 struct pattern_info *pattern_table = ddr3_tip_get_pattern_table(); in ddr3_tip_ip_training() local
398 pattern_table[pattern].start_addr); in ddr3_tip_ip_training()
400 pattern_table[pattern].tx_burst_size : 0; in ddr3_tip_ip_training()
405 pattern_table[pattern].num_of_phases_tx, tx_burst_size, in ddr3_tip_ip_training()
406 pattern_table[pattern].num_of_phases_rx, in ddr3_tip_ip_training()
574 struct pattern_info *pattern_table = ddr3_tip_get_pattern_table(); in ddr3_tip_load_pattern_to_odpg() local
578 pattern_length_cnt < pattern_table[pattern].pattern_len; in ddr3_tip_load_pattern_to_odpg()
875 struct pattern_info *pattern_table = ddr3_tip_get_pattern_table(); in ddr3_tip_load_pattern_to_mem() local
884 0x1 | (pattern_table[pattern].num_of_phases_tx << 5) | in ddr3_tip_load_pattern_to_mem()
885 (pattern_table[pattern].tx_burst_size << 11) | in ddr3_tip_load_pattern_to_mem()
[all …]
Dddr3_training_leveling.c72 struct pattern_info *pattern_table = ddr3_tip_get_pattern_table(); in ddr3_tip_dynamic_read_leveling() local
116 pattern_table[PATTERN_RL].num_of_phases_tx, 0, in ddr3_tip_dynamic_read_leveling()
117 pattern_table[PATTERN_RL].num_of_phases_rx, 0, 0, in ddr3_tip_dynamic_read_leveling()
123 pattern_table[PATTERN_RL]. in ddr3_tip_dynamic_read_leveling()
436 struct pattern_info *pattern_table = ddr3_tip_get_pattern_table(); in ddr3_tip_dynamic_per_bit_read_leveling() local
491 pattern_table[PATTERN_TEST].num_of_phases_tx, 0, in ddr3_tip_dynamic_per_bit_read_leveling()
492 pattern_table[PATTERN_TEST].num_of_phases_rx, 0, in ddr3_tip_dynamic_per_bit_read_leveling()
498 pattern_table[PATTERN_TEST]. in ddr3_tip_dynamic_per_bit_read_leveling()
1399 struct pattern_info *pattern_table = ddr3_tip_get_pattern_table(); in ddr3_tip_xsb_compare_test() local
1418 ((pattern_table[PATTERN_TEST].start_addr << 3) + in ddr3_tip_xsb_compare_test()
Dddr3_init.h59 extern struct pattern_info pattern_table[];