Home
last modified time | relevance | path

Searched refs:phase_min (Results 1 – 1 of 1) sorted by relevance

/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_read_leveling.c405 u32 phase_min, ui_max_delay; in ddr3_read_leveling_single_cs_rl_mode() local
686 phase_min = 10; in ddr3_read_leveling_single_cs_rl_mode()
689 if (dram_info->rl_val[cs][pup][PS] < phase_min) in ddr3_read_leveling_single_cs_rl_mode()
690 phase_min = dram_info->rl_val[cs][pup][PS]; in ddr3_read_leveling_single_cs_rl_mode()
700 switch (phase_min) { in ddr3_read_leveling_single_cs_rl_mode()
718 add = (add >> (phase_min * REG_TRAINING_DEBUG_3_OFFS)); in ddr3_read_leveling_single_cs_rl_mode()
757 u32 delay_s, delay_e, tmp, phase_min, ui_max_delay; in ddr3_read_leveling_single_cs_window_mode() local
1089 phase_min = 10; in ddr3_read_leveling_single_cs_window_mode()
1125 if (phase < phase_min) /* for the read ready delay */ in ddr3_read_leveling_single_cs_window_mode()
1126 phase_min = phase; in ddr3_read_leveling_single_cs_window_mode()
[all …]