| /external/u-boot/drivers/usb/host/ |
| D | ehci-mx6.c | 131 void __iomem *phy_ctrl; in usb_phy_enable() local
139 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); in usb_phy_enable()
154 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); in usb_phy_enable()
158 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); in usb_phy_enable()
164 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 | in usb_phy_enable()
173 void __iomem *phy_ctrl; in usb_phy_mode() local
177 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); in usb_phy_mode()
179 val = readl(phy_ctrl); in usb_phy_mode()
437 void *__iomem phy_ctrl, *__iomem phy_status; in ehci_usb_phy_mode() local
458 phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL); in ehci_usb_phy_mode()
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| D | ehci-vf.c | 87 void __iomem *phy_ctrl; in usb_phy_enable() local
91 phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL); in usb_phy_enable()
104 setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST); in usb_phy_enable()
108 clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST); in usb_phy_enable()
115 setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 | in usb_phy_enable()
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| /external/u-boot/arch/arm/mach-exynos/ |
| D | dmc_init_ddr3.c | 281 *phy_ctrl) in dmc_get_read_offset_value()
283 return readl(&phy_ctrl->phy_con4); in dmc_get_read_offset_value()
291 static void ddr_phy_set_do_resync(struct exynos5420_phy_control *phy_ctrl) in ddr_phy_set_do_resync() argument
293 setbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3); in ddr_phy_set_do_resync()
294 clrbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3); in ddr_phy_set_do_resync()
305 static void dmc_set_read_offset_value(struct exynos5420_phy_control *phy_ctrl, in dmc_set_read_offset_value() argument
308 writel(offset, &phy_ctrl->phy_con4); in dmc_set_read_offset_value()
309 ddr_phy_set_do_resync(phy_ctrl); in dmc_set_read_offset_value()
351 void test_shifts(struct exynos5420_phy_control *phy_ctrl, int ch, in test_shifts() argument
360 dmc_set_read_offset_value(phy_ctrl, DEFAULT_DQS_X4); in test_shifts()
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| /external/u-boot/arch/arm/mach-aspeed/ast2500/ |
| D | sdram_ast2500.c | 97 writel(0, ®s->phy_ctrl[0]); in ast2500_ddr_phy_init_process()
100 writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]); in ast2500_ddr_phy_init_process()
101 while ((readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT)) in ast2500_ddr_phy_init_process()
104 ®s->phy_ctrl[0]); in ast2500_ddr_phy_init_process()
109 writel(0, &info->regs->phy_ctrl[0]); in ast2500_sdrammc_set_vref()
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| /external/u-boot/doc/device-tree-bindings/phy/ |
| D | sun4i-usb-phy.txt | 18 * "phy_ctrl"
53 reg-names = "phy_ctrl", "pmu1", "pmu2";
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| /external/u-boot/drivers/net/ |
| D | e1000.c | 2413 uint32_t phy_ctrl = 0; in e1000_set_d3_lplu_state() local
2435 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); in e1000_set_d3_lplu_state()
2453 phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU; in e1000_set_d3_lplu_state()
2454 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); in e1000_set_d3_lplu_state()
2505 phy_ctrl |= E1000_PHY_CTRL_NOND0A_LPLU; in e1000_set_d3_lplu_state()
2506 E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl); in e1000_set_d3_lplu_state()
2548 uint32_t phy_ctrl = 0; in e1000_set_d0_lplu_state() local
2557 phy_ctrl = E1000_READ_REG(hw, PHY_CTRL); in e1000_set_d0_lplu_state()
2559 phy_ctrl = E1000_READ_REG(hw, I210_PHY_CTRL); in e1000_set_d0_lplu_state()
2569 phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU; in e1000_set_d0_lplu_state()
[all …]
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| /external/u-boot/arch/arm/include/asm/arch-aspeed/ |
| D | sdram_ast2500.h | 120 u32 phy_ctrl[4]; member
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| /external/u-boot/arch/arm/dts/ |
| D | sun8i-a23.dtsi | 87 reg-names = "phy_ctrl", "pmu1";
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| D | sun8i-v3s.dtsi | 173 reg-names = "phy_ctrl",
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| D | sun8i-a83t.dtsi | 243 reg-names = "phy_ctrl",
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| D | sun8i-a33.dtsi | 489 reg-names = "phy_ctrl", "pmu1";
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| D | sun50i-a64.dtsi | 192 reg-names = "phy_ctrl",
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| D | sun8i-h3.dtsi | 242 reg-names = "phy_ctrl",
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| D | sun5i.dtsi | 498 reg-names = "phy_ctrl", "pmu1";
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| D | am33xx.dtsi | 500 reg-names = "phy_ctrl", "wakeup";
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| D | sun6i-a31.dtsi | 569 reg-names = "phy_ctrl",
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| D | sun5i-gr8.dtsi | 707 reg-names = "phy_ctrl", "pmu1";
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| D | sun4i-a10.dtsi | 867 reg-names = "phy_ctrl", "pmu1", "pmu2";
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| D | sun7i-a20.dtsi | 996 reg-names = "phy_ctrl", "pmu1", "pmu2";
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| /external/u-boot/arch/arm/mach-exynos/include/mach/ |
| D | dp.h | 192 unsigned int phy_ctrl; member
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