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Searched refs:phydev (Results 1 – 25 of 142) sorted by relevance

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/external/u-boot/drivers/net/phy/
Dmarvell.c106 static int m88e1xxx_phy_extread(struct phy_device *phydev, int addr, in m88e1xxx_phy_extread() argument
109 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE); in m88e1xxx_phy_extread()
112 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr); in m88e1xxx_phy_extread()
113 val = phy_read(phydev, MDIO_DEVAD_NONE, regnum); in m88e1xxx_phy_extread()
114 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage); in m88e1xxx_phy_extread()
119 static int m88e1xxx_phy_extwrite(struct phy_device *phydev, int addr, in m88e1xxx_phy_extwrite() argument
122 int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE); in m88e1xxx_phy_extwrite()
124 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr); in m88e1xxx_phy_extwrite()
125 phy_write(phydev, MDIO_DEVAD_NONE, regnum, val); in m88e1xxx_phy_extwrite()
126 phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage); in m88e1xxx_phy_extwrite()
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Dbroadcom.c37 static void bcm_phy_write_misc(struct phy_device *phydev, in bcm_phy_write_misc() argument
42 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, in bcm_phy_write_misc()
45 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL); in bcm_phy_write_misc()
47 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg_val); in bcm_phy_write_misc()
50 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, reg_val); in bcm_phy_write_misc()
52 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, value); in bcm_phy_write_misc()
56 static int bcm5461_config(struct phy_device *phydev) in bcm5461_config() argument
58 genphy_config_aneg(phydev); in bcm5461_config()
60 phy_reset(phydev); in bcm5461_config()
65 static int bcm54xx_parse_status(struct phy_device *phydev) in bcm54xx_parse_status() argument
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Dphy.c37 static int genphy_config_advert(struct phy_device *phydev) in genphy_config_advert() argument
44 phydev->advertising &= phydev->supported; in genphy_config_advert()
45 advertise = phydev->advertising; in genphy_config_advert()
48 adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE); in genphy_config_advert()
74 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE, adv); in genphy_config_advert()
81 bmsr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); in genphy_config_advert()
93 adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); in genphy_config_advert()
101 if (phydev->supported & (SUPPORTED_1000baseT_Half | in genphy_config_advert()
112 err = phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, adv); in genphy_config_advert()
126 static int genphy_setup_forced(struct phy_device *phydev) in genphy_setup_forced() argument
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Drealtek.c61 static int rtl8211b_probe(struct phy_device *phydev) in rtl8211b_probe() argument
64 phydev->flags |= PHY_RTL8211x_FORCE_MASTER; in rtl8211b_probe()
70 static int rtl8211e_probe(struct phy_device *phydev) in rtl8211e_probe() argument
73 phydev->flags |= PHY_RTL8211E_PINE64_GIGABIT_FIX; in rtl8211e_probe()
80 static int rtl8211x_config(struct phy_device *phydev) in rtl8211x_config() argument
82 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in rtl8211x_config()
87 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_RTL8211x_PHY_INER, in rtl8211x_config()
90 if (phydev->flags & PHY_RTL8211x_FORCE_MASTER) { in rtl8211x_config()
93 reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); in rtl8211x_config()
98 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, reg); in rtl8211x_config()
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Dmv88e61xx.c216 __weak int mv88e61xx_hw_reset(struct phy_device *phydev) in mv88e61xx_hw_reset() argument
255 static int mv88e61xx_reg_read(struct phy_device *phydev, int dev, int reg) in mv88e61xx_reg_read() argument
257 struct mv88e61xx_phy_priv *priv = phydev->priv; in mv88e61xx_reg_read()
291 static int mv88e61xx_reg_write(struct phy_device *phydev, int dev, int reg, in mv88e61xx_reg_write() argument
294 struct mv88e61xx_phy_priv *priv = phydev->priv; in mv88e61xx_reg_write()
330 static int mv88e61xx_phy_wait(struct phy_device *phydev) in mv88e61xx_phy_wait() argument
336 val = mv88e61xx_reg_read(phydev, DEVADDR_GLOBAL_2, in mv88e61xx_phy_wait()
350 struct phy_device *phydev; in mv88e61xx_phy_read_indirect() local
353 phydev = (struct phy_device *)smi_wrapper->priv; in mv88e61xx_phy_read_indirect()
356 res = mv88e61xx_reg_write(phydev, DEVADDR_GLOBAL_2, in mv88e61xx_phy_read_indirect()
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Datheros.c19 static int ar8021_config(struct phy_device *phydev) in ar8021_config() argument
21 phy_write(phydev, MDIO_DEVAD_NONE, 0x00, 0x1200); in ar8021_config()
22 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); in ar8021_config()
23 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); in ar8021_config()
25 phydev->supported = phydev->drv->features; in ar8021_config()
29 static int ar8031_config(struct phy_device *phydev) in ar8031_config() argument
31 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || in ar8031_config()
32 phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { in ar8031_config()
33 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, in ar8031_config()
35 phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, in ar8031_config()
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Dmicrel_ksz90x1.c42 static int ksz90xx_startup(struct phy_device *phydev) in ksz90xx_startup() argument
47 ret = genphy_update_link(phydev); in ksz90xx_startup()
51 phy_ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ90xx_PHY_CTL); in ksz90xx_startup()
54 phydev->duplex = DUPLEX_FULL; in ksz90xx_startup()
56 phydev->duplex = DUPLEX_HALF; in ksz90xx_startup()
59 phydev->speed = SPEED_1000; in ksz90xx_startup()
61 phydev->speed = SPEED_100; in ksz90xx_startup()
63 phydev->speed = SPEED_10; in ksz90xx_startup()
106 static int ksz90x1_of_config_group(struct phy_device *phydev, in ksz90x1_of_config_group() argument
109 struct udevice *dev = phydev->dev; in ksz90x1_of_config_group()
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Dvitesse.c70 static int vitesse_config(struct phy_device *phydev) in vitesse_config() argument
73 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT, in vitesse_config()
76 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_EXT_CON1, in vitesse_config()
79 genphy_config_aneg(phydev); in vitesse_config()
84 static int vitesse_parse_status(struct phy_device *phydev) in vitesse_parse_status() argument
89 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_CIS82xx_AUX_CONSTAT); in vitesse_parse_status()
92 phydev->duplex = DUPLEX_FULL; in vitesse_parse_status()
94 phydev->duplex = DUPLEX_HALF; in vitesse_parse_status()
99 phydev->speed = SPEED_1000; in vitesse_parse_status()
102 phydev->speed = SPEED_100; in vitesse_parse_status()
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Dmscc.c137 static int mscc_vsc8531_vsc8541_init_scripts(struct phy_device *phydev) in mscc_vsc8531_vsc8541_init_scripts() argument
142 phy_write(phydev, MDIO_DEVAD_NONE, in mscc_vsc8531_vsc8541_init_scripts()
147 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
149 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17); in mscc_vsc8531_vsc8541_init_scripts()
154 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_17, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
155 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
160 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
163 reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18); in mscc_vsc8531_vsc8541_init_scripts()
168 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_DATA_18, reg_val); in mscc_vsc8531_vsc8541_init_scripts()
169 phy_write(phydev, MDIO_DEVAD_NONE, MSCC_PHY_REG_TR_ADDR_16, in mscc_vsc8531_vsc8541_init_scripts()
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Dti.c115 int phy_read_mmd_indirect(struct phy_device *phydev, int prtad, in phy_read_mmd_indirect() argument
121 phy_write(phydev, addr, MII_MMD_CTRL, devad); in phy_read_mmd_indirect()
124 phy_write(phydev, addr, MII_MMD_DATA, prtad); in phy_read_mmd_indirect()
127 phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in phy_read_mmd_indirect()
130 value = phy_read(phydev, addr, MII_MMD_DATA); in phy_read_mmd_indirect()
150 void phy_write_mmd_indirect(struct phy_device *phydev, int prtad, in phy_write_mmd_indirect() argument
154 phy_write(phydev, addr, MII_MMD_CTRL, devad); in phy_write_mmd_indirect()
157 phy_write(phydev, addr, MII_MMD_DATA, prtad); in phy_write_mmd_indirect()
160 phy_write(phydev, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); in phy_write_mmd_indirect()
163 phy_write(phydev, addr, MII_MMD_DATA, data); in phy_write_mmd_indirect()
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Dmeson-gxl.c31 int meson_gxl_startup(struct phy_device *phydev) in meson_gxl_startup() argument
37 ret = genphy_update_link(phydev); in meson_gxl_startup()
41 if (phydev->autoneg == AUTONEG_ENABLE) { in meson_gxl_startup()
43 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); in meson_gxl_startup()
46 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); in meson_gxl_startup()
49 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000); in meson_gxl_startup()
52 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400); in meson_gxl_startup()
57 ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x8D80); in meson_gxl_startup()
62 wol = phy_read(phydev, MDIO_DEVAD_NONE, 0x15); in meson_gxl_startup()
66 lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA); in meson_gxl_startup()
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Daquantia.c22 int aquantia_config(struct phy_device *phydev) in aquantia_config() argument
24 u32 val = phy_read(phydev, MDIO_MMD_PMAPMD, MII_BMCR); in aquantia_config()
26 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { in aquantia_config()
28 phydev->advertising = SUPPORTED_1000baseT_Full; in aquantia_config()
29 phydev->supported = phydev->advertising; in aquantia_config()
32 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, val); in aquantia_config()
33 } else if (phydev->interface == PHY_INTERFACE_MODE_XGMII) { in aquantia_config()
35 phydev->advertising = SUPPORTED_10000baseT_Full; in aquantia_config()
36 phydev->supported = phydev->advertising; in aquantia_config()
40 phy_write(phydev, MDIO_MMD_PMAPMD, MII_BMCR, in aquantia_config()
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Dnatsemi.c17 static int dp83630_config(struct phy_device *phydev) in dp83630_config() argument
21 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in dp83630_config()
22 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0x6); in dp83630_config()
23 ptp_coc_reg = phy_read(phydev, MDIO_DEVAD_NONE, in dp83630_config()
26 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PTP_COC_REG, in dp83630_config()
28 phy_write(phydev, MDIO_DEVAD_NONE, DP83630_PHY_PAGESEL_REG, 0); in dp83630_config()
30 genphy_config_aneg(phydev); in dp83630_config()
55 static int dp838xx_config(struct phy_device *phydev) in dp838xx_config() argument
57 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET); in dp838xx_config()
58 genphy_config_aneg(phydev); in dp838xx_config()
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Dxilinx_phy.c35 static int xilinxphy_startup(struct phy_device *phydev) in xilinxphy_startup() argument
44 err = genphy_update_link(phydev); in xilinxphy_startup()
48 if (AUTONEG_ENABLE == phydev->autoneg) { in xilinxphy_startup()
49 status = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA); in xilinxphy_startup()
53 phydev->duplex = DUPLEX_FULL; in xilinxphy_startup()
55 phydev->duplex = DUPLEX_HALF; in xilinxphy_startup()
59 phydev->speed = SPEED_1000; in xilinxphy_startup()
63 phydev->speed = SPEED_100; in xilinxphy_startup()
67 phydev->speed = SPEED_10; in xilinxphy_startup()
71 int bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in xilinxphy_startup()
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Dmicrel_ksz8xxx.c30 static int ksz_genconfig_bcastoff(struct phy_device *phydev) in ksz_genconfig_bcastoff() argument
34 ret = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO); in ksz_genconfig_bcastoff()
38 ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZPHY_OMSO, in ksz_genconfig_bcastoff()
43 return genphy_config(phydev); in ksz_genconfig_bcastoff()
62 static int ksz8051_config(struct phy_device *phydev) in ksz8051_config() argument
67 val = phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO); in ksz8051_config()
69 phy_write(phydev, MDIO_DEVAD_NONE, MII_KSZ8051_PHY_OMSO, val); in ksz8051_config()
71 return genphy_config(phydev); in ksz8051_config()
108 static void ksz8895_write_smireg(struct phy_device *phydev, int smireg, int val) in ksz8895_write_smireg() argument
110 phydev->bus->write(phydev->bus, smireg_to_phy(smireg), MDIO_DEVAD_NONE, in ksz8895_write_smireg()
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Dgeneric_10g.c16 int gen10g_shutdown(struct phy_device *phydev) in gen10g_shutdown() argument
21 int gen10g_startup(struct phy_device *phydev) in gen10g_startup() argument
24 u32 mmd_mask = phydev->mmds & MDIO_DEVS_LINK; in gen10g_startup()
26 phydev->link = 1; in gen10g_startup()
29 phydev->speed = SPEED_10000; in gen10g_startup()
30 phydev->duplex = DUPLEX_FULL; in gen10g_startup()
42 phy_read(phydev, devad, MDIO_STAT1); in gen10g_startup()
43 reg = phy_read(phydev, devad, MDIO_STAT1); in gen10g_startup()
45 phydev->link = 0; in gen10g_startup()
51 int gen10g_discover_mmds(struct phy_device *phydev) in gen10g_discover_mmds() argument
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Det1011c.c27 static int et1011c_config(struct phy_device *phydev) in et1011c_config() argument
30 ctl = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); in et1011c_config()
36 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, ctl | BMCR_RESET); in et1011c_config()
38 return genphy_config_aneg(phydev); in et1011c_config()
41 static int et1011c_parse_status(struct phy_device *phydev) in et1011c_parse_status() argument
46 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_STATUS_REG); in et1011c_parse_status()
49 phydev->duplex = DUPLEX_FULL; in et1011c_parse_status()
51 phydev->duplex = DUPLEX_HALF; in et1011c_parse_status()
56 phydev->speed = SPEED_1000; in et1011c_parse_status()
57 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, ET1011C_CONFIG_REG); in et1011c_parse_status()
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Dteranetics.c16 int tn2020_config(struct phy_device *phydev) in tn2020_config() argument
18 if (phydev->port == PORT_FIBRE) { in tn2020_config()
30 phy_hwversion = (phy_read(phydev, 30, 32) >> 12) & 0xf; in tn2020_config()
32 phy_write(phydev, 30, 93, 2); in tn2020_config()
33 phy_write(phydev, MDIO_MMD_AN, MDIO_CTRL1, restart_an); in tn2020_config()
35 phy_write(phydev, 30, 93, 1); in tn2020_config()
42 int tn2020_startup(struct phy_device *phydev) in tn2020_startup() argument
57 int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_LNSTAT); in tn2020_startup()
60 "address %u\n", phydev->addr); in tn2020_startup()
73 "align.\n", phydev->addr); in tn2020_startup()
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Dcortina.c125 void cs4340_upload_firmware(struct phy_device *phydev) in cs4340_upload_firmware() argument
216 phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value); in cs4340_upload_firmware()
221 int cs4340_phy_init(struct phy_device *phydev) in cs4340_phy_init() argument
236 phy_write(phydev, 0x00, VILLA_GLOBAL_MSEQCLKCTRL, 0x0004); in cs4340_phy_init()
237 phy_write(phydev, 0x00, VILLA_GLOBAL_LINE_SOFT_RESET, 0x0000); in cs4340_phy_init()
238 phy_write(phydev, 0x00, VILLA_GLOBAL_BIST_CONTROL, 0x0001); in cs4340_phy_init()
240 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS); in cs4340_phy_init()
254 cs4340_upload_firmware(phydev); in cs4340_phy_init()
256 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS); in cs4340_phy_init()
265 int cs4340_config(struct phy_device *phydev) in cs4340_config() argument
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Ddavicom.c26 static int dm9161_config(struct phy_device *phydev) in dm9161_config() argument
28 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_ISOLATE); in dm9161_config()
30 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCR, in dm9161_config()
33 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_10BTCSR, in dm9161_config()
36 genphy_config_aneg(phydev); in dm9161_config()
41 static int dm9161_parse_status(struct phy_device *phydev) in dm9161_parse_status() argument
45 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_DM9161_SCSR); in dm9161_parse_status()
48 phydev->speed = SPEED_100; in dm9161_parse_status()
50 phydev->speed = SPEED_10; in dm9161_parse_status()
53 phydev->duplex = DUPLEX_FULL; in dm9161_parse_status()
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Dlxt.c20 static int lxt971_parse_status(struct phy_device *phydev) in lxt971_parse_status() argument
25 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_LXT971_SR2); in lxt971_parse_status()
30 phydev->speed = SPEED_10; in lxt971_parse_status()
31 phydev->duplex = DUPLEX_HALF; in lxt971_parse_status()
34 phydev->speed = SPEED_10; in lxt971_parse_status()
35 phydev->duplex = DUPLEX_FULL; in lxt971_parse_status()
38 phydev->speed = SPEED_100; in lxt971_parse_status()
39 phydev->duplex = DUPLEX_HALF; in lxt971_parse_status()
42 phydev->speed = SPEED_100; in lxt971_parse_status()
43 phydev->duplex = DUPLEX_FULL; in lxt971_parse_status()
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Dfixed.c16 int fixedphy_probe(struct phy_device *phydev) in fixedphy_probe() argument
19 int ofnode = phydev->addr; in fixedphy_probe()
35 phydev->priv = priv; in fixedphy_probe()
43 phydev->flags |= PHY_FLAG_BROKEN_RESET; in fixedphy_probe()
48 int fixedphy_startup(struct phy_device *phydev) in fixedphy_startup() argument
50 struct fixed_link *priv = phydev->priv; in fixedphy_startup()
52 phydev->asym_pause = priv->asym_pause; in fixedphy_startup()
53 phydev->pause = priv->pause; in fixedphy_startup()
54 phydev->duplex = priv->duplex; in fixedphy_startup()
55 phydev->speed = priv->link_speed; in fixedphy_startup()
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/external/u-boot/include/
Dphy.h141 int (*probe)(struct phy_device *phydev);
145 int (*config)(struct phy_device *phydev);
148 int (*startup)(struct phy_device *phydev);
151 int (*shutdown)(struct phy_device *phydev);
153 int (*readext)(struct phy_device *phydev, int addr, int devad, int reg);
154 int (*writeext)(struct phy_device *phydev, int addr, int devad, int reg,
203 static inline int phy_read(struct phy_device *phydev, int devad, int regnum) in phy_read() argument
205 struct mii_dev *bus = phydev->bus; in phy_read()
207 return bus->read(bus, phydev->addr, devad, regnum); in phy_read()
210 static inline int phy_write(struct phy_device *phydev, int devad, int regnum, in phy_write() argument
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/external/u-boot/board/spear/x600/
Dx600.c71 int board_phy_config(struct phy_device *phydev) in board_phy_config() argument
76 id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); in board_phy_config()
77 id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); in board_phy_config()
83 phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, 0x1c00); in board_phy_config()
86 ksz9031_phy_extended_write(phydev, 0x02, in board_phy_config()
91 ksz9031_phy_extended_write(phydev, 0x02, in board_phy_config()
96 ksz9031_phy_extended_write(phydev, 0x02, in board_phy_config()
101 ksz9031_phy_extended_write(phydev, 0x02, in board_phy_config()
110 phy_write(phydev, MDIO_DEVAD_NONE, 23, 0x0020); in board_phy_config()
113 phy_reset(phydev); in board_phy_config()
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/external/u-boot/board/compulab/cl-som-imx7/
Dcl-som-imx7.c128 static void cl_som_imx7_rgmii_rework(struct phy_device *phydev) in cl_som_imx7_rgmii_rework() argument
135 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3); in cl_som_imx7_rgmii_rework()
136 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); in cl_som_imx7_rgmii_rework()
137 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); in cl_som_imx7_rgmii_rework()
138 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in cl_som_imx7_rgmii_rework()
140 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); in cl_som_imx7_rgmii_rework()
143 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); in cl_som_imx7_rgmii_rework()
144 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); in cl_som_imx7_rgmii_rework()
145 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); in cl_som_imx7_rgmii_rework()
147 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); in cl_som_imx7_rgmii_rework()
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