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Searched refs:pll4_periph0_cfg (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-sunxi/
Dclock_sun9i.c168 &ccm->pll4_periph0_cfg); in clock_set_pll4()
202 uint32_t rval = readl(&ccm->pll4_periph0_cfg); in clock_get_pll4_periph0()
/external/u-boot/arch/arm/include/asm/arch-sunxi/
Dclock_sun9i.h15 u32 pll4_periph0_cfg; /* 0x0c peripheral0 pll configuration */ member