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Searched refs:pll_base (Results 1 – 7 of 7) sorted by relevance

/external/u-boot/arch/arm/mach-davinci/
Dcpu.c60 unsigned int pll_base; in clk_get() local
68 pll_base = (unsigned int)davinci_pllc1_regs; in clk_get()
70 pll_base = (unsigned int)davinci_pllc0_regs; in clk_get()
78 pre_div = (readl(pll_base + PLLC_PREDIV) & in clk_get()
80 pllm = readl(pll_base + PLLC_PLLM) + 1; in clk_get()
88 post_div = (readl(pll_base + PLLC_POSTDIV) & in clk_get()
96 pll_out /= (readl(pll_base + sysdiv[id - 1]) & in clk_get()
/external/u-boot/arch/arm/mach-tegra/
Dcpu.c179 if (readl(&pll->pll_base) & PLL_ENABLE_MASK) { in pllx_set_rate()
189 writel(reg, &pll->pll_base); in pllx_set_rate()
207 reg = readl(&pll->pll_base); in pllx_set_rate()
209 writel(reg, &pll->pll_base); in pllx_set_rate()
220 reg = readl(&pll->pll_base); in pllx_set_rate()
222 writel(reg, &pll->pll_base); in pllx_set_rate()
Dclock.c101 data = readl(&pll->pll_base); in clock_ll_read_pll()
153 writel(data, &pll->pll_base); in clock_start_pll()
156 writel(data, &simple_pll->pll_base); in clock_start_pll()
549 base = readl(&pll->pll_base); in clock_get_rate()
596 base_reg = readl(&pll->pll_base); in clock_set_rate()
615 if (base_reg != readl(&pll->pll_base)) in clock_set_rate()
623 writel(base_reg, &pll->pll_base); in clock_set_rate()
633 writel(base_reg, &pll->pll_base); in clock_set_rate()
637 writel(base_reg, &pll->pll_base); in clock_set_rate()
675 u32 reg = readl(&pll->pll_base); in clock_verify()
/external/u-boot/arch/arm/mach-tegra/tegra20/
Dwarmboot_avp.c188 writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); in wb_start()
191 writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); in wb_start()
193 writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); in wb_start()
/external/u-boot/arch/arm/include/asm/arch-tegra/
Dclk_rst.h12 uint pll_base; /* the control register */ member
20 uint pll_base; /* the control register */ member
/external/u-boot/arch/arm/mach-tegra/tegra124/
Dcpu.c54 reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); in enable_cpu_clocks()
/external/u-boot/arch/arm/mach-tegra/tegra114/
Dcpu.c61 reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); in enable_cpu_clocks()