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Searched refs:pll_div (Results 1 – 16 of 16) sorted by relevance

/external/u-boot/arch/arm/mach-davinci/
Dcpu.c115 static unsigned pll_div(volatile void *pllbase, unsigned offset) in pll_div() function
130 return pll_div(pllbase, PLLC_PREDIV); in pll_prediv()
132 return pll_div(pllbase, PLLC_PREDIV); in pll_prediv()
140 return pll_div(pllbase, PLLC_POSTDIV); in pll_postdiv()
143 return pll_div(pllbase, PLLC_POSTDIV); in pll_postdiv()
167 return DIV_ROUND_UP(base, 1000 * pll_div(pllbase, div)); in pll_sysclk_mhz()
/external/u-boot/drivers/clk/rockchip/
Dclk_rk3368.c29 struct pll_div { struct
50 static const struct pll_div apll_l_init_cfg = PLL_DIVISORS(APLL_L_HZ, 12, 2); argument
51 static const struct pll_div apll_b_init_cfg = PLL_DIVISORS(APLL_B_HZ, 1, 2);
53 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2);
54 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 6);
89 const struct pll_div *div) in rkclk_set_pll()
284 const struct pll_div *dpll_cfg = NULL; in rk3368_ddr_set_clk()
288 static const struct pll_div dpll_1200 = PLL_DIVISORS(1200 * MHz, 1, 1); in rk3368_ddr_set_clk()
289 static const struct pll_div dpll_1332 = PLL_DIVISORS(1332 * MHz, 2, 1); in rk3368_ddr_set_clk()
290 static const struct pll_div dpll_1600 = PLL_DIVISORS(1600 * MHz, 3, 2); in rk3368_ddr_set_clk()
Dclk_rk3399.c32 struct pll_div { struct
50 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); argument
51 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2, 2);
53 static const struct pll_div ppll_init_cfg = PLL_DIVISORS(PPLL_HZ, 2, 2, 1);
56 static const struct pll_div apll_l_1600_cfg = PLL_DIVISORS(1600*MHz, 3, 1, 1);
57 static const struct pll_div apll_l_600_cfg = PLL_DIVISORS(600*MHz, 1, 2, 1);
59 static const struct pll_div *apll_l_cfgs[] = {
291 static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) in rkclk_set_pll()
334 static int pll_para_config(u32 freq_hz, struct pll_div *div) in pll_para_config()
620 struct pll_div vpll_config = {0}; in rk3399_vop_set_clk()
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Dclk_rk322x.c38 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
39 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
42 const struct pll_div *div) in rkclk_set_pll()
319 struct pll_div dpll_cfg; in rk322x_ddr_set_clk()
324 dpll_cfg = (struct pll_div) in rk322x_ddr_set_clk()
328 dpll_cfg = (struct pll_div) in rk322x_ddr_set_clk()
332 dpll_cfg = (struct pll_div) in rk322x_ddr_set_clk()
Dclk_rk3328.c20 struct pll_div { struct
37 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1); argument
38 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 2, 1);
40 static const struct pll_div apll_816_cfg = PLL_DIVISORS(816 * MHz, 1, 2, 1);
41 static const struct pll_div apll_600_cfg = PLL_DIVISORS(600 * MHz, 1, 3, 1);
43 static const struct pll_div *apll_cfgs[] = {
207 const struct pll_div *div) in rkclk_set_pll()
Dclk_rk3188.c36 struct pll_div { struct
81 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
82 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
86 const struct pll_div *div, bool has_bwadj) in rkclk_set_pll()
122 static const struct pll_div dpll_cfg[] = { in rkclk_configure_ddr()
168 static const struct pll_div apll_cfg[] = { in rkclk_configure_cpu()
Dclk_rk3288.c33 struct pll_div { struct
139 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1);
140 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2);
141 static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2);
144 const struct pll_div *div) in rkclk_set_pll()
177 static const struct pll_div dpll_cfg[] = { in rkclk_configure_ddr()
226 static int pll_para_config(ulong freq_hz, struct pll_div *div, uint *ext_div) in pll_para_config()
338 struct pll_div npll_config = {0}; in rockchip_vop_set_clk()
Dclk_rk3128.c35 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
36 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
39 const struct pll_div *div) in rkclk_set_pll()
76 static int pll_para_config(u32 freq_hz, struct pll_div *div) in pll_para_config()
419 struct pll_div cpll_config = {0}; in rk3128_vop_set_clk()
Dclk_rk3036.c41 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
42 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
45 const struct pll_div *div) in rkclk_set_pll()
/external/u-boot/arch/arm/mach-imx/mx7/
Dclock.c775 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom, in enable_pll_video() argument
782 pll_div, pll_num, pll_denom); in enable_pll_video()
796 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | in enable_pll_video()
802 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | in enable_pll_video()
808 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | in enable_pll_video()
814 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | in enable_pll_video()
821 writel(CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(pll_div) | in enable_pll_video()
898 u32 pll_div, pll_num, pll_denom, post_div = 0; in mxs_set_lcdclk() local
942 pll_div = best / hck; in mxs_set_lcdclk()
944 pll_num = (best - hck * pll_div) * pll_denom / hck; in mxs_set_lcdclk()
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/external/u-boot/arch/arm/mach-imx/mx6/
Dclock.c551 static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom, in enable_pll_video() argument
558 pll_div, pll_num, pll_denom); in enable_pll_video()
570 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) | in enable_pll_video()
575 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) | in enable_pll_video()
580 writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) | in enable_pll_video()
626 u32 pll_div, pll_num, pll_denom, post_div = 1; in mxs_set_lcdclk() local
697 pll_div = best / hck; in mxs_set_lcdclk()
699 pll_num = (best - hck * pll_div) * pll_denom / hck; in mxs_set_lcdclk()
710 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) in mxs_set_lcdclk()
747 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) in mxs_set_lcdclk()
/external/u-boot/arch/arm/include/asm/arch-rockchip/
Dcru_rv1108.h49 struct pll_div { struct
Dcru_rk3036.h60 struct pll_div { struct
Dcru_rk322x.h61 struct pll_div { struct
Dcru_rk3128.h63 struct pll_div { struct
/external/u-boot/arch/arm/mach-rockchip/rk3036/
Dsdram_rk3036.c40 const struct pll_div dpll_init_cfg = {1, 66, 2, 1};