Searched refs:pll_enet (Results 1 – 6 of 6) sorted by relevance
144 reg = readl(&ccm_anatop->pll_enet); in decode_pll()300 reg = readl(&ccm_anatop->pll_enet); in mxc_get_pll_enet_derive()743 reg = readl(&ccm_anatop->pll_enet); in enable_pll_enet()747 writel(reg, &ccm_anatop->pll_enet); in enable_pll_enet()750 if (readl(&ccm_anatop->pll_enet) & ANADIG_PLL_LOCK) in enable_pll_enet()
284 reg = readl(&anatop->pll_enet); in setup_fec()286 writel(reg, &anatop->pll_enet); in setup_fec()
133 reg = readl(&anatop->pll_enet); in setup_fec()135 writel(reg, &anatop->pll_enet); in setup_fec()
916 reg = readl(&anatop->pll_enet); in enable_fec_anatop_clock()934 writel(reg, &anatop->pll_enet); in enable_fec_anatop_clock()936 if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK) in enable_fec_anatop_clock()949 writel(reg, &anatop->pll_enet); in enable_fec_anatop_clock()
867 u32 pll_enet; /* 0x0e0 */ member
112 uint32_t pll_enet; /* offset 0x00e0 */ member