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Searched refs:pll_enet_clr (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/arch/arm/mach-imx/mx7/
Dclock.c762 writel(CCM_ANALOG_PLL_ENET_BYPASS_MASK, &ccm_anatop->pll_enet_clr); in enable_pll_enet()
/external/u-boot/arch/arm/include/asm/arch-mx6/
Dimx-regs.h869 u32 pll_enet_clr; /* 0x0e8 */ member
/external/u-boot/arch/arm/include/asm/arch-mx7/
Dcrm_regs.h114 uint32_t pll_enet_clr; member