| /external/u-boot/arch/arm/mach-tegra/ |
| D | clock.c | 25 static unsigned pll_rate[CLOCK_ID_COUNT]; variable
274 div = clk_get_divider(8, pll_rate[clkid], rate); in clock_set_pllout()
313 unsigned parent_rate = pll_rate[parent]; in clock_get_periph_rate()
451 divider = find_best_divider(divider_bits, pll_rate[parent], in clock_adjust_periph_pll_div()
689 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL); in clock_init()
690 pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY); in clock_init()
691 pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH); in clock_init()
692 pll_rate[CLOCK_ID_USB] = clock_get_rate(CLOCK_ID_USB); in clock_init()
693 pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY); in clock_init()
694 pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU); in clock_init()
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| /external/u-boot/drivers/clk/rockchip/ |
| D | clk_rv1108.c | 89 ulong pll_rate; in rv1108_mac_set_clk() local
93 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_mac_set_clk()
95 pll_rate = rkclk_pll_get_rate(cru, CLK_ARM); in rv1108_mac_set_clk()
101 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rv1108_mac_set_clk()
108 return DIV_TO_RATE(pll_rate, div); in rv1108_mac_set_clk()
114 u32 pll_rate; in rv1108_sfc_set_clk() local
118 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_sfc_set_clk()
120 pll_rate = rkclk_pll_get_rate(cru, CLK_DDR); in rv1108_sfc_set_clk()
122 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rv1108_sfc_set_clk()
129 return DIV_TO_RATE(pll_rate, div); in rv1108_sfc_set_clk()
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| D | clk_rk3368.c | 160 u32 pll_rate; in rk3368_mmc_get_clk() local
179 pll_rate = rkclk_pll_get_rate(cru, GPLL); in rk3368_mmc_get_clk()
182 pll_rate = OSC_HZ; in rk3368_mmc_get_clk()
185 pll_rate = rkclk_pll_get_rate(cru, CPLL); in rk3368_mmc_get_clk()
192 rate = DIV_TO_RATE(pll_rate, div); in rk3368_mmc_get_clk()
325 ulong pll_rate; in rk3368_gmac_set_clk() local
330 pll_rate = GPLL_HZ; in rk3368_gmac_set_clk()
333 pll_rate = CPLL_HZ; in rk3368_gmac_set_clk()
338 div = DIV_ROUND_UP(pll_rate, set_rate) - 1; in rk3368_gmac_set_clk()
345 return DIV_TO_RATE(pll_rate, div); in rk3368_gmac_set_clk()
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| D | clk_rk3328.c | 419 ulong pll_rate; in rk3328_gmac2io_set_clk() local
423 pll_rate = GPLL_HZ; in rk3328_gmac2io_set_clk()
425 pll_rate = CPLL_HZ; in rk3328_gmac2io_set_clk()
427 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rk3328_gmac2io_set_clk()
434 return DIV_TO_RATE(pll_rate, div); in rk3328_gmac2io_set_clk()
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| D | clk_rk322x.c | 252 ulong pll_rate; in rk322x_mac_set_clk() local
256 pll_rate = GPLL_HZ; in rk322x_mac_set_clk()
261 div = DIV_ROUND_UP(pll_rate, freq) - 1; in rk322x_mac_set_clk()
268 return DIV_TO_RATE(pll_rate, div); in rk322x_mac_set_clk()
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| D | clk_rk3288.c | 310 ulong pll_rate; in rockchip_mac_set_clk() local
315 pll_rate = GPLL_HZ; in rockchip_mac_set_clk()
318 pll_rate = CPLL_HZ; in rockchip_mac_set_clk()
320 pll_rate = NPLL_HZ; in rockchip_mac_set_clk()
322 div = DIV_ROUND_UP(pll_rate, freq) - 1; in rockchip_mac_set_clk()
329 return DIV_TO_RATE(pll_rate, div); in rockchip_mac_set_clk()
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| /external/u-boot/drivers/clk/ |
| D | clk-hsdk-cgu.c | 136 const u32 pll_rate[MAX_TUN_CLOCKS]; member
156 const u32 pll_rate[MAX_AXI_CLOCKS]; member
538 ulong pll_rate; in axi_clk_set() local
542 pll_rate = pll_get(sclk); in axi_clk_set()
557 if (axi_clk_cfg.pll_rate[freq_idx] < pll_rate) in axi_clk_set()
558 ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]); in axi_clk_set()
567 if (axi_clk_cfg.pll_rate[freq_idx] >= pll_rate) in axi_clk_set()
568 ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]); in axi_clk_set()
576 ulong pll_rate; in tun_clk_set() local
580 pll_rate = pll_get(sclk); in tun_clk_set()
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| D | clk_zynq.c | 288 ulong pll_rate, in zynq_clk_calc_peripheral_two_divs() argument
298 DIV_ROUND_CLOSEST(pll_rate, d0), d1); in zynq_clk_calc_peripheral_two_divs()
319 ulong pll_rate, new_rate; in zynq_clk_set_peripheral_rate() local
326 pll_rate = zynq_clk_get_pll_rate(priv, pll); in zynq_clk_set_peripheral_rate()
330 new_rate = zynq_clk_calc_peripheral_two_divs(rate, pll_rate, in zynq_clk_set_peripheral_rate()
334 div0 = DIV_ROUND_CLOSEST(pll_rate, rate); in zynq_clk_set_peripheral_rate()
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| D | clk_zynqmp.c | 492 ulong pll_rate, in zynqmp_clk_calc_peripheral_two_divs() argument
502 DIV_ROUND_CLOSEST(pll_rate, d0), d1); in zynqmp_clk_calc_peripheral_two_divs()
523 ulong pll_rate, new_rate; in zynqmp_clk_set_peripheral_rate() local
536 pll_rate = zynqmp_clk_get_pll_rate(priv, pll); in zynqmp_clk_set_peripheral_rate()
537 if (IS_ERR_VALUE(pll_rate)) in zynqmp_clk_set_peripheral_rate()
538 return pll_rate; in zynqmp_clk_set_peripheral_rate()
543 new_rate = zynqmp_clk_calc_peripheral_two_divs(rate, pll_rate, in zynqmp_clk_set_peripheral_rate()
547 div0 = DIV_ROUND_CLOSEST(pll_rate, rate); in zynqmp_clk_set_peripheral_rate()
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