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Searched refs:pll_regs (Results 1 – 6 of 6) sorted by relevance

/external/u-boot/arch/arm/cpu/arm926ejs/mx27/
Dgeneric.c46 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in clk_in_26m()
58 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_mpllclk()
72 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_armclk()
87 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_ahbclk()
99 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_spllclk()
118 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk1()
125 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk2()
132 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk3()
139 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in imx_get_perclk4()
181 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in cpu_eth_init()
Dtimer.c91 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in timer_init()
/external/u-boot/arch/mips/mach-ath79/ar934x/
Dclk.c107 void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE, in ar934x_pll_init() local
167 setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
169 setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
171 setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
176 pll_regs + AR934X_PLL_CPU_CONFIG_REG); in ar934x_pll_init()
179 pll_regs + AR934X_PLL_DDR_CONFIG_REG); in ar934x_pll_init()
190 pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG); in ar934x_pll_init()
197 clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
199 clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
201 clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
[all …]
/external/u-boot/arch/arm/lib/
Dasm-offsets.c80 DEFINE(CSCR, IMX_PLL_BASE + offsetof(struct pll_regs, cscr)); in main()
81 DEFINE(MPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, mpctl0)); in main()
82 DEFINE(SPCTL0, IMX_PLL_BASE + offsetof(struct pll_regs, spctl0)); in main()
83 DEFINE(PCDR0, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr0)); in main()
84 DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1)); in main()
85 DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0)); in main()
86 DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1)); in main()
/external/u-boot/board/armadeus/apf27/
Dfpga.c193 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE; in apf27_fpga_setup()
/external/u-boot/arch/arm/include/asm/arch-mx27/
Dimx-regs.h114 struct pll_regs { struct