Searched refs:pll_set (Results 1 – 1 of 1) sorted by relevance
| /external/u-boot/drivers/clk/ |
| D | clk-hsdk-cgu.c | 271 static ulong pll_set(struct clk *, ulong);
285 { CGU_ARC_PLL, 0, 0, &core_pll_dat, pll_get, pll_set, NULL },
287 { CGU_DDR_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
288 { CGU_SYS_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
305 { CGU_TUN_PLL, 0, 0, &sdt_pll_dat, pll_get, pll_set, NULL },
309 { CGU_HDMI_PLL, 0, 0, &hdmi_pll_dat, pll_get, pll_set, NULL },
477 static ulong pll_set(struct clk *sclk, ulong rate) in pll_set() function
528 ret = pll_set(sclk, rate); in cpu_clk_set()
558 ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]); in axi_clk_set()
568 ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]); in axi_clk_set()
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