Searched refs:pll_stable_status (Results 1 – 4 of 4) sorted by relevance
28 while (!(readl(&ccm->pll_stable_status) & (1 << 8))) {} in clock_init_safe()40 while (!(readl(&ccm->pll_stable_status) & (1 << 6))) {} in clock_init_safe()91 while (!(readl(&ccm->pll_stable_status) & 0x01)) {} in clock_set_pll1()96 while (!(readl(&ccm->pll_stable_status) & 0x02)) {} in clock_set_pll1()
142 do { } while (!(readl(&ccm->pll_stable_status) & PLL_DDR_STATUS)); in clock_set_pll6()
40 u32 pll_stable_status; /* 0x9c */ member
93 u32 pll_stable_status; /* 0x20c PLL stable status register */ member