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Searched refs:pll_video (Results 1 – 3 of 3) sorted by relevance

/external/u-boot/arch/arm/mach-imx/mx7/
Dclock.c838 reg = readl(&ccm_anatop->pll_video); in enable_pll_video()
/external/u-boot/arch/arm/include/asm/arch-mx6/
Dimx-regs.h855 u32 pll_video; /* 0x0a0 */ member
/external/u-boot/arch/arm/include/asm/arch-mx7/
Dcrm_regs.h126 uint32_t pll_video; /* offset 0x0130 */ member