Searched refs:pllcfgr (Results 1 – 3 of 3) sorted by relevance
| /external/u-boot/drivers/clk/ |
| D | clk_stm32f.c | 156 writel(0x24003010, ®s->pllcfgr); /* Reset value from RM */ in configure_clocks()
171 setbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */ in configure_clocks()
172 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLM_MASK, in configure_clocks()
174 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLN_MASK, in configure_clocks()
176 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLP_MASK, in configure_clocks()
178 clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLQ_MASK, in configure_clocks()
280 pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); in stm32_clk_get_pllsai_vco_rate()
405 pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK); in stm32_clk_get_rate()
406 plln = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLN_MASK) in stm32_clk_get_rate()
408 pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) in stm32_clk_get_rate()
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| D | clk_stm32h7.c | 131 u32 pllcfgr; /* 0x2c PLLs Configuration Register */ member
352 uint32_t pllcfgr = 0; in configure_clocks() local
403 pllcfgr |= PLL1RGE_4_8_MHZ << RCC_PLLCFGR_PLL1RGE_SHIFT; in configure_clocks()
404 pllcfgr |= RCC_PLLCFGR_DIVP1EN; in configure_clocks()
405 pllcfgr |= RCC_PLLCFGR_DIVQ1EN; in configure_clocks()
406 pllcfgr |= RCC_PLLCFGR_DIVR1EN; in configure_clocks()
407 writel(pllcfgr, ®s->pllcfgr); in configure_clocks()
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| /external/u-boot/include/ |
| D | stm32_rcc.h | 60 u32 pllcfgr; /* RCC PLL configuration */ member
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