| /external/libdrm/tests/amdgpu/ |
| D | basic_tests.c | 530 uint32_t *pm4; in amdgpu_bo_eviction_test() local
540 pm4 = calloc(pm4_dw, sizeof(*pm4)); in amdgpu_bo_eviction_test()
541 CU_ASSERT_NOT_EQUAL(pm4, NULL); in amdgpu_bo_eviction_test()
616 pm4[i++] = SDMA_PACKET_SI(SDMA_OPCODE_COPY_SI, 0, 0, 0, in amdgpu_bo_eviction_test()
618 pm4[i++] = 0xffffffff & bo2_mc; in amdgpu_bo_eviction_test()
619 pm4[i++] = 0xffffffff & bo1_mc; in amdgpu_bo_eviction_test()
620 pm4[i++] = (0xffffffff00000000 & bo2_mc) >> 32; in amdgpu_bo_eviction_test()
621 pm4[i++] = (0xffffffff00000000 & bo1_mc) >> 32; in amdgpu_bo_eviction_test()
623 pm4[i++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0); in amdgpu_bo_eviction_test()
625 pm4[i++] = sdma_write_length - 1; in amdgpu_bo_eviction_test()
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| /external/ltp/testcases/kernel/mem/mem/ |
| D | mem02.c | 68 char *pm1, *pm2, *pm3, *pm4; in main() local
151 pm4 = pm3 = malloc(10); in main()
153 *pm4++ = 'X'; in main()
156 pm4 = realloc(pm3, 5); in main()
157 pm6 = (long)pm4; in main()
158 pm3 = pm4; in main()
161 if (*pm4++ != 'X') { in main()
170 pm4 = realloc(pm3, 15); in main()
172 pm3 = pm4; in main()
182 free(pm4); in main()
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_state_shaders.c | 326 struct si_pm4_state *pm4) in si_set_tesseval_regs() argument
384 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM, in si_set_tesseval_regs()
408 struct si_pm4_state *pm4) in polaris_set_vgt_vertex_reuse() argument
428 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, in polaris_set_vgt_vertex_reuse()
435 if (shader->pm4) in si_get_shader_pm4_state()
436 si_pm4_clear_state(shader->pm4); in si_get_shader_pm4_state()
438 shader->pm4 = CALLOC_STRUCT(si_pm4_state); in si_get_shader_pm4_state()
440 return shader->pm4; in si_get_shader_pm4_state()
445 struct si_pm4_state *pm4; in si_shader_ls() local
451 pm4 = si_get_shader_pm4_state(shader); in si_shader_ls()
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| D | si_state.c | 472 struct si_pm4_state *pm4 = &blend->pm4; in si_create_blend_state_mode() local
490 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, in si_create_blend_state_mode()
527 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); in si_create_blend_state_mode()
538 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); in si_create_blend_state_mode()
548 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); in si_create_blend_state_mode()
612 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl); in si_create_blend_state_mode()
645 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4, in si_create_blend_state_mode()
654 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control); in si_create_blend_state_mode()
861 struct si_pm4_state *pm4 = &rs->pm4; in si_create_rs_state() local
897 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, in si_create_rs_state()
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| D | si_pm4.c | 37 state->pm4[state->ndw++] = dw; in si_pm4_cmd_add()
44 state->pm4[state->last_pm4] = in si_pm4_cmd_end()
134 radeon_emit_array(cs, state->pm4, state->ndw); in si_pm4_emit()
180 state->pm4[i] = 0x80000000; /* type2 nop packet */ in si_pm4_upload_indirect_buffer()
183 state->pm4[i] = 0xffff1000; /* type3 nop packet */ in si_pm4_upload_indirect_buffer()
187 0, aligned_ndw *4, state->pm4); in si_pm4_upload_indirect_buffer()
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| D | si_state.h | 47 struct si_pm4_state pm4; member
63 struct si_pm4_state pm4; member
110 struct si_pm4_state pm4; member
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| D | si_pm4.h | 47 uint32_t pm4[SI_PM4_MAX_DW]; member
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| D | si_shader.h | 592 struct si_pm4_state *pm4; member
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| D | si_debug.c | 353 ac_parse_ib(f, ctx->init_config->pm4, ctx->init_config->ndw, in si_log_chunk_type_cs_print()
358 ac_parse_ib(f, ctx->init_config_gs_rings->pm4, in si_log_chunk_type_cs_print()
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| /external/clang/test/CXX/temp/temp.arg/temp.arg.nontype/ |
| D | p1-11.cpp | 43 PM<(int X::*)0> pm4; variable
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