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1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright 2007,2009-2012 Freescale Semiconductor, Inc.
4  */
5 
6 #ifndef __FSL_PCI_H_
7 #define __FSL_PCI_H_
8 
9 #include <asm/fsl_law.h>
10 #include <asm/fsl_serdes.h>
11 #include <pci.h>
12 
13 #define PEX_IP_BLK_REV_2_2	0x02080202
14 #define PEX_IP_BLK_REV_2_3	0x02080203
15 #define PEX_IP_BLK_REV_3_0	0x02080300
16 
17 /* Freescale-specific PCI config registers */
18 #define FSL_PCI_PBFR		0x44
19 
20 #define FSL_PCIE_CFG_RDY	0x4b0
21 #define FSL_PCIE_V3_CFG_RDY	0x1
22 #define FSL_PROG_IF_AGENT	0x1
23 
24 #define PCI_LTSSM	0x404   /* PCIe Link Training, Status State Machine */
25 #define  PCI_LTSSM_L0	0x16    /* L0 state */
26 
27 int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
28 int fsl_is_pci_agent(struct pci_controller *hose);
29 void fsl_pci_config_unlock(struct pci_controller *hose);
30 void ft_fsl_pci_setup(void *blob, const char *compat, unsigned long ctrl_addr);
31 
32 /*
33  * Common PCI/PCIE Register structure for mpc85xx and mpc86xx
34  */
35 
36 /*
37  * PCI Translation Registers
38  */
39 typedef struct pci_outbound_window {
40 	u32	potar;		/* 0x00 - Address */
41 	u32	potear;		/* 0x04 - Address Extended */
42 	u32	powbar;		/* 0x08 - Window Base Address */
43 	u32	res1;
44 	u32	powar;		/* 0x10 - Window Attributes */
45 #define POWAR_EN	0x80000000
46 #define POWAR_IO_READ	0x00080000
47 #define POWAR_MEM_READ	0x00040000
48 #define POWAR_IO_WRITE	0x00008000
49 #define POWAR_MEM_WRITE	0x00004000
50 	u32	res2[3];
51 } pot_t;
52 
53 typedef struct pci_inbound_window {
54 	u32	pitar;		/* 0x00 - Address */
55 	u32	res1;
56 	u32	piwbar;		/* 0x08 - Window Base Address */
57 	u32	piwbear;	/* 0x0c - Window Base Address Extended */
58 	u32	piwar;		/* 0x10 - Window Attributes */
59 #define PIWAR_EN		0x80000000
60 #define PIWAR_PF		0x20000000
61 #define PIWAR_LOCAL		0x00f00000
62 #define PIWAR_READ_SNOOP	0x00050000
63 #define PIWAR_WRITE_SNOOP	0x00005000
64 	u32	res2[3];
65 } pit_t;
66 
67 /* PCI/PCI Express Registers */
68 typedef struct ccsr_pci {
69 	u32	cfg_addr;	/* 0x000 - PCI Configuration Address Register */
70 	u32	cfg_data;	/* 0x004 - PCI Configuration Data Register */
71 	u32	int_ack;	/* 0x008 - PCI Interrupt Acknowledge Register */
72 	u32	out_comp_to;	/* 0x00C - PCI Outbound Completion Timeout Register */
73 	u32	out_conf_to;	/* 0x010 - PCI Configuration Timeout Register */
74 	u32	config;		/* 0x014 - PCIE CONFIG Register */
75 	u32	int_status;	/* 0x018 - PCIE interrupt status register */
76 	char	res2[4];
77 	u32	pme_msg_det;	/* 0x020 - PCIE PME & message detect register */
78 	u32	pme_msg_dis;	/* 0x024 - PCIE PME & message disable register */
79 	u32	pme_msg_int_en;	/* 0x028 - PCIE PME & message interrupt enable register */
80 	u32	pm_command;	/* 0x02c - PCIE PM Command register */
81 	char	res3[2188];	/*     (0x8bc - 0x30 = 2188) */
82 	u32	dbi_ro_wr_en;	/* 0x8bc - DBI read only write enable reg */
83 	char	res4[824];	/*     (0xbf8 - 0x8c0 = 824) */
84 	u32	block_rev1;	/* 0xbf8 - PCIE Block Revision register 1 */
85 	u32	block_rev2;	/* 0xbfc - PCIE Block Revision register 2 */
86 
87 	pot_t	pot[5];		/* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */
88 	u32	res5[24];
89 	pit_t	pmit;		/* 0xd00 - 0xd9c Inbound ATMU's MSI */
90 	u32	res6[24];
91 	pit_t	pit[4];		/* 0xd80 - 0xdff Inbound ATMU's 3, 2, 1 and 0 */
92 
93 #define PIT3 0
94 #define PIT2 1
95 #define PIT1 2
96 
97 #if 0
98 	u32	potar0;		/* 0xc00 - PCI Outbound Transaction Address Register 0 */
99 	u32	potear0;	/* 0xc04 - PCI Outbound Translation Extended Address Register 0 */
100 	char	res5[8];
101 	u32	powar0;		/* 0xc10 - PCI Outbound Window Attributes Register 0 */
102 	char	res6[12];
103 	u32	potar1;		/* 0xc20 - PCI Outbound Transaction Address Register 1 */
104 	u32	potear1;	/* 0xc24 - PCI Outbound Translation Extended Address Register 1 */
105 	u32	powbar1;	/* 0xc28 - PCI Outbound Window Base Address Register 1 */
106 	char	res7[4];
107 	u32	powar1;		/* 0xc30 - PCI Outbound Window Attributes Register 1 */
108 	char	res8[12];
109 	u32	potar2;		/* 0xc40 - PCI Outbound Transaction Address Register 2 */
110 	u32	potear2;	/* 0xc44 - PCI Outbound Translation Extended Address Register 2 */
111 	u32	powbar2;	/* 0xc48 - PCI Outbound Window Base Address Register 2 */
112 	char	res9[4];
113 	u32	powar2;		/* 0xc50 - PCI Outbound Window Attributes Register 2 */
114 	char	res10[12];
115 	u32	potar3;		/* 0xc60 - PCI Outbound Transaction Address Register 3 */
116 	u32	potear3;	/* 0xc64 - PCI Outbound Translation Extended Address Register 3 */
117 	u32	powbar3;	/* 0xc68 - PCI Outbound Window Base Address Register 3 */
118 	char	res11[4];
119 	u32	powar3;		/* 0xc70 - PCI Outbound Window Attributes Register 3 */
120 	char	res12[12];
121 	u32	potar4;		/* 0xc80 - PCI Outbound Transaction Address Register 4 */
122 	u32	potear4;	/* 0xc84 - PCI Outbound Translation Extended Address Register 4 */
123 	u32	powbar4;	/* 0xc88 - PCI Outbound Window Base Address Register 4 */
124 	char	res13[4];
125 	u32	powar4;		/* 0xc90 - PCI Outbound Window Attributes Register 4 */
126 	char	res14[268];
127 	u32	pitar3;		/* 0xda0 - PCI Inbound Translation Address Register 3 */
128 	char	res15[4];
129 	u32	piwbar3;	/* 0xda8 - PCI Inbound Window Base Address Register 3 */
130 	u32	piwbear3;	/* 0xdac - PCI Inbound Window Base Extended Address Register 3 */
131 	u32	piwar3;		/* 0xdb0 - PCI Inbound Window Attributes Register 3 */
132 	char	res16[12];
133 	u32	pitar2;		/* 0xdc0 - PCI Inbound Translation Address Register 2 */
134 	char	res17[4];
135 	u32	piwbar2;	/* 0xdc8 - PCI Inbound Window Base Address Register 2 */
136 	u32	piwbear2;	/* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */
137 	u32	piwar2;		/* 0xdd0 - PCI Inbound Window Attributes Register 2 */
138 	char	res18[12];
139 	u32	pitar1;		/* 0xde0 - PCI Inbound Translation Address Register 1 */
140 	char	res19[4];
141 	u32	piwbar1;	/* 0xde8 - PCI Inbound Window Base Address Register 1 */
142 	char	res20[4];
143 	u32	piwar1;		/* 0xdf0 - PCI Inbound Window Attributes Register 1 */
144 	char	res21[12];
145 #endif
146 	u32	pedr;		/* 0xe00 - PCI Error Detect Register */
147 	u32	pecdr;		/* 0xe04 - PCI Error Capture Disable Register */
148 	u32	peer;		/* 0xe08 - PCI Error Interrupt Enable Register */
149 	u32	peattrcr;	/* 0xe0c - PCI Error Attributes Capture Register */
150 	u32	peaddrcr;	/* 0xe10 - PCI Error Address Capture Register */
151 /*	u32	perr_disr	 * 0xe10 - PCIE Erorr Disable Register */
152 	u32	peextaddrcr;	/* 0xe14 - PCI	Error Extended Address Capture Register */
153 	u32	pedlcr;		/* 0xe18 - PCI Error Data Low Capture Register */
154 	u32	pedhcr;		/* 0xe1c - PCI Error Error Data High Capture Register */
155 	u32	gas_timr;	/* 0xe20 - PCI Gasket Timer Register */
156 /*	u32	perr_cap_stat;	 * 0xe20 - PCIE Error Capture Status Register */
157 	char	res22[4];
158 	u32	perr_cap0;	/* 0xe28 - PCIE Error Capture Register 0 */
159 	u32	perr_cap1;	/* 0xe2c - PCIE Error Capture Register 1 */
160 	u32	perr_cap2;	/* 0xe30 - PCIE Error Capture Register 2 */
161 	u32	perr_cap3;	/* 0xe34 - PCIE Error Capture Register 3 */
162 	char	res23[200];
163 	u32	pdb_stat;	/* 0xf00 - PCIE Debug Status */
164 	char	res24[16];
165 	u32	pex_csr0;	/* 0xf14 - PEX Control/Status register 0*/
166 	u32	pex_csr1;	/* 0xf18 - PEX Control/Status register 1*/
167 	char	res25[228];
168 } ccsr_fsl_pci_t;
169 #define PCIE_CONFIG_PC	0x00020000
170 #define PCIE_CONFIG_OB_CK	0x00002000
171 #define PCIE_CONFIG_SAC	0x00000010
172 #define PCIE_CONFIG_SP	0x80000002
173 #define PCIE_CONFIG_SCC	0x80000001
174 
175 struct fsl_pci_info {
176 	unsigned long regs;
177 	pci_addr_t mem_bus;
178 	phys_size_t mem_phys;
179 	pci_size_t mem_size;
180 	pci_addr_t io_bus;
181 	phys_size_t io_phys;
182 	pci_size_t io_size;
183 	enum law_trgt_if law;
184 	int pci_num;
185 };
186 
187 void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info);
188 int fsl_pci_init_port(struct fsl_pci_info *pci_info,
189 				struct pci_controller *hose, int busno);
190 int fsl_pcie_init_ctrl(int busno, u32 devdisr, enum srds_prtcl dev,
191 			struct fsl_pci_info *pci_info);
192 int fsl_pcie_init_board(int busno);
193 
194 #define SET_STD_PCI_INFO(x, num) \
195 {			\
196 	x.regs = CONFIG_SYS_PCI##num##_ADDR;	\
197 	x.mem_bus = CONFIG_SYS_PCI##num##_MEM_BUS; \
198 	x.mem_phys = CONFIG_SYS_PCI##num##_MEM_PHYS; \
199 	x.mem_size = CONFIG_SYS_PCI##num##_MEM_SIZE; \
200 	x.io_bus = CONFIG_SYS_PCI##num##_IO_BUS; \
201 	x.io_phys = CONFIG_SYS_PCI##num##_IO_PHYS; \
202 	x.io_size = CONFIG_SYS_PCI##num##_IO_SIZE; \
203 	x.law = LAW_TRGT_IF_PCI_##num; \
204 	x.pci_num = num; \
205 }
206 
207 #define SET_STD_PCIE_INFO(x, num) \
208 {			\
209 	x.regs = CONFIG_SYS_PCIE##num##_ADDR;	\
210 	x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \
211 	x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \
212 	x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \
213 	x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \
214 	x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \
215 	x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \
216 	x.law = LAW_TRGT_IF_PCIE_##num; \
217 	x.pci_num = num; \
218 }
219 
220 #define __FT_FSL_PCI_SETUP(blob, compat, num) \
221 	ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCI##num##_ADDR)
222 
223 #define __FT_FSL_PCIE_SETUP(blob, compat, num) \
224 	ft_fsl_pci_setup(blob, compat, CONFIG_SYS_PCIE##num##_ADDR)
225 
226 #define FT_FSL_PCI1_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 1)
227 #define FT_FSL_PCI2_SETUP __FT_FSL_PCI_SETUP(blob, FSL_PCI_COMPAT, 2)
228 
229 #define FT_FSL_PCIE1_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 1)
230 #define FT_FSL_PCIE2_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 2)
231 #define FT_FSL_PCIE3_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 3)
232 #define FT_FSL_PCIE4_SETUP __FT_FSL_PCIE_SETUP(blob, FSL_PCIE_COMPAT, 4)
233 
234 #if !defined(CONFIG_PCI)
235 #define FT_FSL_PCI_SETUP
236 #elif defined(CONFIG_FSL_CORENET)
237 #define FSL_PCIE_COMPAT	CONFIG_SYS_FSL_PCIE_COMPAT
238 #define FT_FSL_PCI_SETUP \
239 	FT_FSL_PCIE1_SETUP; \
240 	FT_FSL_PCIE2_SETUP; \
241 	FT_FSL_PCIE3_SETUP; \
242 	FT_FSL_PCIE4_SETUP;
243 #define FT_FSL_PCIE_SETUP FT_FSL_PCI_SETUP
244 #elif defined(CONFIG_MPC85xx)
245 #define FSL_PCI_COMPAT	"fsl,mpc8540-pci"
246 #ifdef CONFIG_SYS_FSL_PCIE_COMPAT
247 #define FSL_PCIE_COMPAT	CONFIG_SYS_FSL_PCIE_COMPAT
248 #else
249 #define FSL_PCIE_COMPAT	"fsl,mpc8548-pcie"
250 #endif
251 #define FT_FSL_PCI_SETUP \
252 	FT_FSL_PCI1_SETUP; \
253 	FT_FSL_PCI2_SETUP; \
254 	FT_FSL_PCIE1_SETUP; \
255 	FT_FSL_PCIE2_SETUP; \
256 	FT_FSL_PCIE3_SETUP;
257 #define FT_FSL_PCIE_SETUP \
258 	FT_FSL_PCIE1_SETUP; \
259 	FT_FSL_PCIE2_SETUP; \
260 	FT_FSL_PCIE3_SETUP;
261 #elif defined(CONFIG_MPC86xx)
262 #define FSL_PCI_COMPAT	"fsl,mpc8610-pci"
263 #define FSL_PCIE_COMPAT	"fsl,mpc8641-pcie"
264 #define FT_FSL_PCI_SETUP \
265 	FT_FSL_PCI1_SETUP; \
266 	FT_FSL_PCIE1_SETUP; \
267 	FT_FSL_PCIE2_SETUP;
268 #else
269 #error FT_FSL_PCI_SETUP not defined
270 #endif
271 
272 
273 #endif
274