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Searched refs:pmu_spare2 (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/mach-exynos/
Ddmc_init_ddr3.c804 dmc_set_read_offset_value(phy1_ctrl, readl(&pmu->pmu_spare2)); in ddr3_mem_ctrl_init()
812 writel(dmc_get_read_offset_value(phy1_ctrl), &pmu->pmu_spare2); in ddr3_mem_ctrl_init()
/external/u-boot/arch/arm/mach-exynos/include/mach/
Dpower.h292 unsigned int pmu_spare2; member
916 unsigned int pmu_spare2; /* Store PHY1_CON4 for read leveling */ member