| /external/u-boot/drivers/clk/aspeed/ |
| D | clk_ast2500.c | 45 unsigned int post_div; member
57 const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK) in ast2500_get_mpll_rate() local
60 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); in ast2500_get_mpll_rate()
72 const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK) in ast2500_get_hpll_rate() local
75 return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1); in ast2500_get_hpll_rate()
193 for (it.post_div = 0; it.post_div <= max_vals.post_div; in ast2500_calc_clock_config()
194 ++it.post_div) { in ast2500_calc_clock_config()
195 it.num = (rate_khz * (it.post_div + 1) / input_rate_khz) in ast2500_calc_clock_config()
202 / (it.post_div + 1); in ast2500_calc_clock_config()
227 .post_div = (SCU_MPLL_POST_MASK >> SCU_MPLL_POST_SHIFT), in ast2500_configure_ddr()
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| /external/u-boot/drivers/spi/ |
| D | mxc_spi.c | 135 u32 pre_div = 0, post_div = 0; in spi_cfg_mxc() local
153 post_div = fls(pre_div); in spi_cfg_mxc()
154 if (post_div > 4) { in spi_cfg_mxc()
155 post_div -= 4; in spi_cfg_mxc()
156 if (post_div >= 16) { in spi_cfg_mxc()
161 pre_div >>= post_div; in spi_cfg_mxc()
163 post_div = 0; in spi_cfg_mxc()
167 debug("pre_div = %d, post_div=%d\n", pre_div, post_div); in spi_cfg_mxc()
173 MXC_CSPICTRL_POSTDIV(post_div); in spi_cfg_mxc()
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| /external/u-boot/arch/arm/mach-davinci/ |
| D | cpu.c | 58 int post_div; in clk_get() local
88 post_div = (readl(pll_base + PLLC_POSTDIV) & in clk_get()
91 pll_out /= post_div; in clk_get()
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| /external/u-boot/arch/arm/mach-imx/mx6/ |
| D | clock.c | 552 u32 post_div) in enable_pll_video() argument
568 switch (post_div) { in enable_pll_video()
626 u32 pll_div, pll_num, pll_denom, post_div = 1; in mxs_set_lcdclk() local
663 for (post_div = 2; post_div <= 4; post_div <<= 1) { in mxs_set_lcdclk()
664 if ((temp * post_div) > min) { in mxs_set_lcdclk()
665 freq *= post_div; in mxs_set_lcdclk()
670 if (post_div > 4) { in mxs_set_lcdclk()
710 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) in mxs_set_lcdclk()
747 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) in mxs_set_lcdclk()
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| /external/u-boot/arch/arm/mach-imx/mx7/ |
| D | clock.c | 474 enum root_post_div post_div; in get_ddrc_clk() local
484 post_div = reg & DRAM_CLK_ROOT_POST_DIV_MASK; in get_ddrc_clk()
486 return freq / (post_div + 1) / 2; in get_ddrc_clk()
776 u32 post_div) in enable_pll_video() argument
794 switch (post_div) { in enable_pll_video()
898 u32 pll_div, pll_num, pll_denom, post_div = 0; in mxs_set_lcdclk() local
909 post_div = i; in mxs_set_lcdclk()
946 if (enable_pll_video(pll_div, pll_num, pll_denom, post_div)) in mxs_set_lcdclk()
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| D | clock_slice.c | 672 enum root_post_div post_div, enum clk_root_src clock_src) in clock_root_cfg() argument
698 if (post_div > CLK_ROOT_POST_DIV7) { in clock_root_cfg()
705 if (post_div != CLK_ROOT_POST_DIV1) { in clock_root_cfg()
716 post_div << CLK_ROOT_POST_DIV_SHIFT | in clock_root_cfg()
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| /external/u-boot/board/gdsys/common/ |
| D | osd.c | 80 unsigned int *post_div, unsigned int *feedback_div) in mpc92469ac_calc_parameters() argument
82 unsigned int n = *post_div; in mpc92469ac_calc_parameters()
100 *post_div = n; in mpc92469ac_calc_parameters()
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| /external/u-boot/arch/arm/include/asm/arch-mx7/ |
| D | clock_slice.h | 111 enum root_post_div post_div, enum clk_root_src clock_src);
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| /external/u-boot/arch/arm/mach-imx/mx8m/ |
| D | clock_slice.c | 670 enum root_post_div *post_div) in clock_get_postdiv() argument
688 *post_div = 0; in clock_get_postdiv()
707 *post_div = val; in clock_get_postdiv()
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| /external/u-boot/arch/arm/include/asm/arch-mx8m/ |
| D | clock.h | 644 enum root_post_div post_div, enum clk_root_src clock_src);
649 enum root_post_div *post_div);
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| /external/u-boot/drivers/video/ |
| D | ati_radeon_fb.h | 224 int post_div; member
|