Searched refs:pp_txfilter (Results 1 – 8 of 8) sorted by relevance
64 t->pp_txfilter &= ~(RADEON_CLAMP_S_MASK | RADEON_CLAMP_T_MASK | RADEON_BORDER_MODE_D3D); in radeonSetTexWrap()68 t->pp_txfilter |= RADEON_CLAMP_S_WRAP; in radeonSetTexWrap()71 t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_GL; in radeonSetTexWrap()75 t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_LAST; in radeonSetTexWrap()78 t->pp_txfilter |= RADEON_CLAMP_S_CLAMP_GL; in radeonSetTexWrap()82 t->pp_txfilter |= RADEON_CLAMP_S_MIRROR; in radeonSetTexWrap()85 t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_GL; in radeonSetTexWrap()89 t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_LAST; in radeonSetTexWrap()92 t->pp_txfilter |= RADEON_CLAMP_S_MIRROR_CLAMP_GL; in radeonSetTexWrap()102 t->pp_txfilter |= RADEON_CLAMP_T_WRAP; in radeonSetTexWrap()[all …]
606 t->pp_txfilter |= tx_table[MESA_FORMAT_B8G8R8A8_UNORM].filter; in radeonSetTexBuffer2()612 t->pp_txfilter |= tx_table[MESA_FORMAT_BGR_UNORM8].filter; in radeonSetTexBuffer2()617 t->pp_txfilter |= tx_table[MESA_FORMAT_B5G6R5_UNORM].filter; in radeonSetTexBuffer2()729 cmd[TEX_PP_TXFILTER] |= texobj->pp_txfilter & TEXOBJ_TXFILTER_MASK; in import_tex_obj_state()934 t->pp_txfilter &= ~RADEON_YUV_TO_RGB; in setup_hardware_state()937 t->pp_txfilter |= table[ firstImage->TexFormat ].filter; in setup_hardware_state()945 t->pp_txfilter &= ~RADEON_MAX_MIP_LEVEL_MASK; in setup_hardware_state()946 t->pp_txfilter |= (t->maxLod - t->minLod) << RADEON_MAX_MIP_LEVEL_SHIFT; in setup_hardware_state()1006 if (unit != 0 && (t->pp_txfilter & RADEON_YUV_TO_RGB)) in radeon_validate_texture()
204 GLuint pp_txfilter; /* hardware register values */ member
73 t->pp_txfilter &= ~(R200_CLAMP_S_MASK | R200_CLAMP_T_MASK | R200_BORDER_MODE_D3D); in r200SetTexWrap()77 t->pp_txfilter |= R200_CLAMP_S_WRAP; in r200SetTexWrap()80 t->pp_txfilter |= R200_CLAMP_S_CLAMP_GL; in r200SetTexWrap()84 t->pp_txfilter |= R200_CLAMP_S_CLAMP_LAST; in r200SetTexWrap()87 t->pp_txfilter |= R200_CLAMP_S_CLAMP_GL; in r200SetTexWrap()91 t->pp_txfilter |= R200_CLAMP_S_MIRROR; in r200SetTexWrap()94 t->pp_txfilter |= R200_CLAMP_S_MIRROR_CLAMP_GL; in r200SetTexWrap()98 t->pp_txfilter |= R200_CLAMP_S_MIRROR_CLAMP_LAST; in r200SetTexWrap()101 t->pp_txfilter |= R200_CLAMP_S_MIRROR_CLAMP_GL; in r200SetTexWrap()111 t->pp_txfilter |= R200_CLAMP_T_WRAP; in r200SetTexWrap()[all …]
700 t->pp_txfilter |= tx_table_le[MESA_FORMAT_B8G8R8A8_UNORM].filter; in r200SetTexBuffer2()706 t->pp_txfilter |= tx_table_le[MESA_FORMAT_BGR_UNORM8].filter; in r200SetTexBuffer2()711 t->pp_txfilter |= tx_table_le[MESA_FORMAT_B5G6R5_UNORM].filter; in r200SetTexBuffer2()986 cmd[TEX_PP_TXFILTER] |= texobj->pp_txfilter & TEXOBJ_TXFILTER_MASK; in import_tex_obj_state()1317 t->pp_txfilter &= ~R200_YUV_TO_RGB; in setup_hardware_state()1320 t->pp_txfilter |= table[ firstImage->TexFormat ].filter; in setup_hardware_state()1330 t->pp_txfilter &= ~R200_MAX_MIP_LEVEL_MASK; in setup_hardware_state()1331 t->pp_txfilter |= ((t->maxLod) << R200_MAX_MIP_LEVEL_SHIFT) in setup_hardware_state()1334 if ( t->pp_txfilter & in setup_hardware_state()
409 unsigned int pp_txfilter; member