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/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DHowToUseInstrMappings.rst65 takes a non-predicated instruction and returns its predicated true or false form
67 to define a relationship model that relates predicated instructions to their
68 non-predicated form by assigning appropriate values to the ``InstrMapping``
69 fields. For this relationship, non-predicated instructions are treated as key
82 // For example, if we want to relate 'ADD' (non-predicated) with 'Add_pt'
83 // (predicated true) and 'Add_pf' (predicated false), then all 3
95 // attribute of the key (non-predicated) and column (true/false)
99 // The key column contains non-predicated instructions.
108 non-predicated instructions with their predicated forms. It also outputs the
113 predicated form of the instruction, if found in the relation table.
/external/llvm/docs/
DHowToUseInstrMappings.rst65 takes a non-predicated instruction and returns its predicated true or false form
67 to define a relationship model that relates predicated instructions to their
68 non-predicated form by assigning appropriate values to the ``InstrMapping``
69 fields. For this relationship, non-predicated instructions are treated as key
82 // For example, if we want to relate 'ADD' (non-predicated) with 'Add_pt'
83 // (predicated true) and 'Add_pf' (predicated false), then all 3
95 // attribute of the key (non-predicated) and column (true/false)
99 // The key column contains non-predicated instructions.
108 non-predicated instructions with their predicated forms. It also outputs the
113 predicated form of the instruction, if found in the relation table.
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Hexagon/
Dnew-value-check.s9 # invalid: r0 definition predicated on the opposite condition
25 # CHECK-STRICT: :28:3: note: Register producer is predicated and consumer is unconditional
40 # CHECK-STRICT: :43:3: note: Register producer is predicated and consumer is unconditional
58 # valid: r0 definition and use identically predicated
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopSimplify/
Dpreserve-scev.ll17 ; CHECK: Loop %for.body18: Unpredictable predicated backedge-taken count.
20 ; CHECK: Loop %for.cond: Unpredictable predicated backedge-taken count.
29 ; CHECK: Loop %for.body18: Unpredictable predicated backedge-taken count.
32 ; CHECK: Loop %for.cond: Unpredictable predicated backedge-taken count.
35 ; CHECK: Loop %for.cond.outer: Unpredictable predicated backedge-taken count.
86 ; CHECK: Loop %while.cond191: Unpredictable predicated backedge-taken count.
89 ; CHECK: Loop %while.cond191.outer: Unpredictable predicated backedge-taken count.
99 ; CHECK: Loop %while.cond191.outer: Unpredictable predicated backedge-taken count.
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopVectorize/AArch64/
Dpredication_costs.ll14 ; This test checks that we correctly compute the cost of the predicated udiv
55 ; This test checks that we correctly compute the cost of the predicated store
91 ; This test checks that we correctly compute the cost of the predicated udiv
93 ; inside the predicated block. If we assume the block probability is 50%, we
136 ; This test checks that we correctly compute the cost of the predicated store
138 ; inside the predicated block. If we assume the block probability is 50%, we
177 ; This test checks that we correctly compute the cost of multiple predicated
179 ; and predicated. The sub feeding the store is scalarized and sunk inside the
180 ; store's predicated block. However, the add feeding the sdiv and udiv cannot
/external/llvm/test/Analysis/ScalarEvolution/
Dpredicated-trip-count.ll17 ; throughout the execution of the loop. The resulting predicated
51 ; The predicated backedge taken count is:
57 ; The predicated backedge taken count is 0.
65 ; The predicated backedge taken count is 1 + (zext i16 %Start to i32) - %M
67 ; If %M >= MIN_INT + 1, this predicated backedge taken count would be correct (even
/external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/ScalarEvolution/
Dpredicated-trip-count.ll17 ; throughout the execution of the loop. The resulting predicated
51 ; The predicated backedge taken count is:
57 ; The predicated backedge taken count is 0.
65 ; The predicated backedge taken count is 1 + (zext i16 %Start to i32) - %M
67 ; If %M >= MIN_INT + 1, this predicated backedge taken count would be correct (even
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dbranch-folder-hoist-kills.mir11 # then created code, where the first predicated instruction has incorrect
18 # %r0 = C2_cmoveit %P0, 2, implicit %r0 ; predicated A2_tfrsi
19 # %r0 = C2_cmoveif killed %P0, 1, implicit %r0 ; predicated A2_tfrsi
Difcvt-live-subreg.mir2 # Check that an implicit use is generated for a predicated instruction
7 # Verify the predicated block:
Difcvt-impuse-livein.mir3 # Make sure that the necessary implicit uses are added to predicated
/external/llvm/lib/Target/Hexagon/
DHexagon.td58 // PredRel - Filter class used to relate non-predicated instructions with their
59 // predicated forms.
61 // PredNewRel - Filter class used to relate predicated instructions with their
77 // predicated formats - true and false.
117 // Generate mapping table to relate predicated instructions with their .new
129 // Generate mapping table to relate .new predicated instructions with their old
/external/deqp-deps/SPIRV-Tools/source/opt/
Dmerge_return_pass.cpp109 std::unordered_set<BasicBlock*> predicated; in ProcessStructured() local
124 if (!PredicateBlocks(block, &predicated, &order)) { in ProcessStructured()
312 BasicBlock* return_block, std::unordered_set<BasicBlock*>* predicated, in PredicateBlocks() argument
317 if (predicated->count(return_block)) { in PredicateBlocks()
343 if (!predicated->insert(block).second) break; in PredicateBlocks()
351 if (!BreakFromConstruct(block, next, predicated, order)) { in PredicateBlocks()
361 std::unordered_set<BasicBlock*>* predicated, in BreakFromConstruct() argument
397 predicated->insert(old_body); in BreakFromConstruct()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagon.td93 // PredRel - Filter class used to relate non-predicated instructions with their
94 // predicated forms.
96 // PredNewRel - Filter class used to relate predicated instructions with their
110 // predicated formats - true and false.
150 // Generate mapping table to relate predicated instructions with their .new
162 // Generate mapping table to relate .new predicated instructions with their old
/external/swiftshader/third_party/SPIRV-Tools/source/opt/
Dmerge_return_pass.cpp109 std::unordered_set<BasicBlock*> predicated; in ProcessStructured() local
124 if (!PredicateBlocks(block, &predicated, &order)) { in ProcessStructured()
312 BasicBlock* return_block, std::unordered_set<BasicBlock*>* predicated, in PredicateBlocks() argument
317 if (predicated->count(return_block)) { in PredicateBlocks()
343 if (!predicated->insert(block).second) break; in PredicateBlocks()
352 if (!BreakFromConstruct(block, predicated, order, in PredicateBlocks()
362 BasicBlock* block, std::unordered_set<BasicBlock*>* predicated, in BreakFromConstruct() argument
403 predicated->insert(old_body); in BreakFromConstruct()
/external/llvm/test/MC/Hexagon/
Dnew-value-check.s9 # invalid: r0 definition predicated on the opposite condition
61 # valid: r0 definition and use identically predicated
/external/swiftshader/third_party/llvm-7.0/llvm/docs/HistoricalNotes/
D2001-02-09-AdveCommentsResponse.txt39 implementation may choose altermate representations (such as predicated
148 > predicated instructions
150 Conditional move is effectly a special case of a predicated
151 instruction... and I think that all predicated instructions can possibly
155 tend to prefer that a predicated architecture like IA64 convert from a
156 "basic block" representation to a predicated rep as part of it's dynamic
/external/swiftshader/third_party/LLVM/docs/HistoricalNotes/
D2001-02-09-AdveCommentsResponse.txt39 implementation may choose altermate representations (such as predicated
148 > predicated instructions
150 Conditional move is effectly a special case of a predicated
151 instruction... and I think that all predicated instructions can possibly
155 tend to prefer that a predicated architecture like IA64 convert from a
156 "basic block" representation to a predicated rep as part of it's dynamic
/external/llvm/docs/HistoricalNotes/
D2001-02-09-AdveCommentsResponse.txt39 implementation may choose altermate representations (such as predicated
148 > predicated instructions
150 Conditional move is effectly a special case of a predicated
151 instruction... and I think that all predicated instructions can possibly
155 tend to prefer that a predicated architecture like IA64 convert from a
156 "basic block" representation to a predicated rep as part of it's dynamic
/external/mesa3d/src/gallium/drivers/freedreno/ir3/
Dir3_sched.c472 struct ir3_instruction *predicated = ir->predicates[i]; in split_pred() local
475 if (is_scheduled(predicated)) in split_pred()
484 if (ssa(predicated->regs[1]) == ctx->pred) { in split_pred()
490 predicated->regs[1]->instr = new_pred; in split_pred()
/external/llvm/test/MC/ELF/ARM/
Dlit.local.cfg2 # predicated on 'X86'.
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ELF/ARM/
Dlit.local.cfg2 # predicated on 'X86'.
/external/mesa3d/src/amd/vulkan/
Dsi_cmd_buffer.c828 bool predicated, in si_cs_emit_write_event_eop() argument
843 radeon_emit(cs, PKT3(PKT3_RELEASE_MEM, is_gfx8_mec ? 5 : 6, predicated)); in si_cs_emit_write_event_eop()
859 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated)); in si_cs_emit_write_event_eop()
867 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, predicated)); in si_cs_emit_write_event_eop()
878 bool predicated, in si_emit_wait_fence() argument
882 radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, predicated)); in si_emit_wait_fence()
894 bool predicated, in si_emit_acquire_mem() argument
900 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, predicated) | in si_emit_acquire_mem()
910 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, predicated)); in si_emit_acquire_mem()
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dinvalid-RFEorLDMIA-arm.txt10 # A8.6.53 LDM/LDMIA/LDMFD is predicated with Inst{31-28} as cond ==> Not an LDMIA instruction
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dimplicit-it.s28 @ THUMB-STDERR: error: predicated instructions must be in IT block
29 @ ARM-STDERR: warning: predicated instructions should be in IT block
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopVectorize/X86/
Dx86-predication.ll9 ; This test ensures that we don't scalarize the predicated load. Since the load
65 ; sink-scalar-operands optimization for predicated instructions.

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