Searched refs:prefx (Results 1 – 19 of 19) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/ |
| D | micromips-control-instructions.s | 53 # CHECK-EL: prefx 1, $3($5) # encoding: [0x65,0x54,0xa0,0x09]
87 # CHECK-EB: prefx 1, $3($5) # encoding: [0x54,0x65,0x09,0xa0]
116 prefx 1, $3($5)
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| D | micromips-invalid.s | 80 prefx -1, $8($5) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
81 prefx 32, $8($5) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
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| /external/llvm/test/MC/Mips/ |
| D | micromips-control-instructions.s | 44 # CHECK-EL: prefx 1, $3($5) # encoding: [0x65,0x54,0xa0,0x09]
86 # CHECK-EB: prefx 1, $3($5) # encoding: [0x54,0x65,0x09,0xa0]
123 prefx 1, $3($5)
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| D | micromips-invalid.s | 80 prefx -1, $8($5) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
81 prefx 32, $8($5) # CHECK: :[[@LINE]]:9: error: expected 5-bit unsigned immediate
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| /external/llvm/test/MC/Mips/mips32r6/ |
| D | invalid-mips4.s | 14 …prefx 0,$2($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips32r6/ |
| D | invalid-mips4.s | 14 …prefx 0,$2($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
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| /external/llvm/test/MC/Mips/mips64r6/ |
| D | invalid-mips4.s | 17 …prefx 0,$2($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/mips64r6/ |
| D | invalid-mips4.s | 17 …prefx 0,$2($31) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
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| /external/google-breakpad/src/third_party/libdisasm/ |
| D | TODO | 37 if ( prefx) only use if insn != invalid
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| /external/u-boot/arch/mips/include/asm/ |
| D | asm.h | 167 prefx hint, addr; \
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Mips/micromips/ |
| D | valid.s | 287 prefx 1, $3($5) # CHECK: prefx 1, $3($5) # encoding: [0x54,0x65,0x09,0xa0] label
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| /external/llvm/test/MC/Disassembler/Mips/micromips32r3/ |
| D | valid-el.txt | 175 0x65 0x54 0xa0 0x09 # CHECK: prefx 1, $3($5)
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| D | valid.txt | 175 0x54 0x65 0x09 0xa0 # CHECK: prefx 1, $3($5)
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Mips/micromips32r3/ |
| D | valid-el.txt | 192 0x65 0x54 0xa0 0x09 # CHECK: prefx 1, $3($5)
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| D | valid.txt | 192 0x54 0x65 0x09 0xa0 # CHECK: prefx 1, $3($5)
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| /external/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrInfo.td | 969 def PREFX_MM : PrefetchIndexed<"prefx">, POOL32F_PREFX_FM_MM<0x15, 0x1A0>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MicroMipsInstrInfo.td | 1115 def PREFX_MM : PrefetchIndexed<"prefx">, POOL32F_PREFX_FM_MM<0x15, 0x1A0>,
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| D | MipsInstrInfo.td | 2519 // FIXME: We are missing the prefx instruction.
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenAsmMatcher.inc | 4979 ".ph.w\017precrqu_s.qb.ph\004pref\005prefe\005prefx\007prepend\nraddu.w."
7039 …{ 7603 /* prefx */, Mips::PREFX_MM, Convert__GPR32AsmReg1_3__GPR32AsmReg1_1__ConstantUImm5_01_0, F…
10456 { Feature_InMicroMips|Feature_NotMips32r6, 7603 /* prefx */, MCK_GPR32AsmReg, 10 /* 1, 3 */ },
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