Searched refs:prev_inst (Results 1 – 5 of 5) sorted by relevance
50 backend_instruction *const prev_inst = prev_block->end(); in dead_control_flow_eliminate() local56 prev_inst->opcode == BRW_OPCODE_ELSE) { in dead_control_flow_eliminate()58 backend_instruction *const else_inst = prev_inst; in dead_control_flow_eliminate()63 prev_inst->opcode == BRW_OPCODE_IF) { in dead_control_flow_eliminate()67 backend_instruction *const if_inst = prev_inst; in dead_control_flow_eliminate()100 prev_inst->opcode == BRW_OPCODE_IF) { in dead_control_flow_eliminate()102 backend_instruction *const if_inst = prev_inst; in dead_control_flow_eliminate()
316 for (vec4_instruction *prev_inst = (vec4_instruction *) inst->prev; in can_use_scratch_for_source() local317 !prev_inst->is_head_sentinel(); in can_use_scratch_for_source()318 prev_inst = (vec4_instruction *) prev_inst->prev) { in can_use_scratch_for_source()324 if (prev_inst->dst.file == VGRF && prev_inst->dst.nr == scratch_reg) { in can_use_scratch_for_source()325 return (!prev_inst->predicate || prev_inst->opcode == BRW_OPCODE_SEL) && in can_use_scratch_for_source()327 ~prev_inst->dst.writemask) == 0; in can_use_scratch_for_source()334 if (prev_inst->opcode == SHADER_OPCODE_GEN4_SCRATCH_WRITE || in can_use_scratch_for_source()335 prev_inst->opcode == SHADER_OPCODE_GEN4_SCRATCH_READ) in can_use_scratch_for_source()343 if (prev_inst->src[n].file == VGRF && in can_use_scratch_for_source()344 prev_inst->src[n].nr == scratch_reg) { in can_use_scratch_for_source()
3131 fs_inst *prev_inst = last_mrf_move[inst->dst.nr]; in remove_duplicate_mrf_writes() local3132 if (prev_inst && inst->equals(prev_inst)) { in remove_duplicate_mrf_writes()
732 struct schedule_node *prev_inst) in choose_instruction_to_schedule() argument740 if (prev_inst) { in choose_instruction_to_schedule()741 if (prev_inst->inst->qpu.sig.thrsw) in choose_instruction_to_schedule()788 if (prev_inst) { in choose_instruction_to_schedule()795 if (prev_inst->inst->uniform != -1 && in choose_instruction_to_schedule()809 &prev_inst->inst->qpu, inst)) { in choose_instruction_to_schedule()1171 vir_for_each_inst_rev(prev_inst, block) { in emit_thrsw()1172 struct v3d_qpu_sig sig = prev_inst->qpu.sig; in emit_thrsw()1179 if (!valid_thrsw_sequence(c, prev_inst, slots_filled + 1, in emit_thrsw()1184 merge_inst = prev_inst; in emit_thrsw()
573 struct schedule_node *prev_inst) in choose_instruction_to_schedule() argument581 if (prev_inst) { in choose_instruction_to_schedule()582 uint32_t prev_sig = QPU_GET_FIELD(prev_inst->inst->inst, in choose_instruction_to_schedule()622 if (prev_inst) { in choose_instruction_to_schedule()631 if (prev_inst->uniform != -1 && n->uniform != -1) in choose_instruction_to_schedule()642 inst = qpu_merge_inst(prev_inst->inst->inst, inst); in choose_instruction_to_schedule()