Home
last modified time | relevance | path

Searched refs:printReg (Results 1 – 25 of 77) sorted by relevance

1234

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DAMDGPUMachineCFGStructurizer.cpp271 dbgs() << "Dest: " << printReg(Element.DestReg, TRI) in dump()
274 dbgs() << printReg(SI.first, TRI) << '(' << printMBBReference(*SI.second) in dump()
504 dbgs() << " In: " << printReg(getBBSelectRegIn(), TRI); in dump()
505 dbgs() << ", Out: " << printReg(getBBSelectRegOut(), TRI) << "\n"; in dump()
554 dbgs() << " In: " << printReg(getBBSelectRegIn(), TRI); in dump()
555 dbgs() << ", Out: " << printReg(getBBSelectRegOut(), TRI) << "\n"; in dump()
699 LLVM_DEBUG(dbgs() << "Considering Register: " << printReg(Reg, TRI) in storeLiveOutReg()
704 LLVM_DEBUG(dbgs() << "Add LiveOut (PHI): " << printReg(Reg, TRI) << "\n"); in storeLiveOutReg()
711 << "): " << printReg(Reg, TRI) << "\n"); in storeLiveOutReg()
722 LLVM_DEBUG(dbgs() << "Add LiveOut (Loop): " << printReg(Reg, TRI) in storeLiveOutReg()
[all …]
DGCNRegPressure.cpp53 dbgs() << " " << printReg(Reg, MRI.getTargetRegisterInfo()) in printLivesAt()
448 dbgs() << " " << printReg(P.first, TRI) in reportMismatch()
453 dbgs() << " " << printReg(P.first, TRI) in reportMismatch()
464 dbgs() << " " << printReg(P.first, TRI) in reportMismatch()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DAggressiveAntiDepBreaker.cpp145 << " " << printReg(r, TRI)); in AggressiveAntiDepBreaker()
220 << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg) in Observe()
327 dbgs() << header << printReg(Reg, TRI); in HandleLastUse()
343 dbgs() << header << printReg(Reg, TRI); in HandleLastUse()
346 LLVM_DEBUG(dbgs() << " " << printReg(SubregReg, TRI) << "->g" in HandleLastUse()
382 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" in PrescanInstruction()
403 << printReg(AliasReg, TRI) << ")"); in PrescanInstruction()
478 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" in ScanInstruction()
514 LLVM_DEBUG(dbgs() << "=" << printReg(Reg, TRI)); in ScanInstruction()
517 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI)); in ScanInstruction()
[all …]
DRegAllocFast.cpp325 LLVM_DEBUG(dbgs() << "Spilling " << printReg(LRI->VirtReg, TRI) << " in " in spillVirtReg()
326 << printReg(LR.PhysReg, TRI)); in spillVirtReg()
481 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) in calcSpillCost()
491 LLVM_DEBUG(dbgs() << printReg(VirtReg, TRI) << " corresponding " in calcSpillCost()
492 << printReg(PhysReg, TRI) << " is reserved already.\n"); in calcSpillCost()
502 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << " is disabled.\n"); in calcSpillCost()
529 LLVM_DEBUG(dbgs() << "Assigning " << printReg(LR.VirtReg, TRI) << " to " in assignVirtToPhysReg()
530 << printReg(PhysReg, TRI) << "\n"); in assignVirtToPhysReg()
576 LLVM_DEBUG(dbgs() << "Allocating " << printReg(VirtReg) << " from " in allocVirtReg()
583 LLVM_DEBUG(dbgs() << "\tRegister: " << printReg(PhysReg, TRI) << "\n"); in allocVirtReg()
[all …]
DLiveRegMatrix.cpp105 LLVM_DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg, TRI) << " to " in assign()
106 << printReg(PhysReg, TRI) << ':'); in assign()
123 LLVM_DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg, TRI) << " from " in unassign()
124 << printReg(PhysReg, TRI) << ':'); in unassign()
DRegAllocGreedy.cpp776 LLVM_DEBUG(dbgs() << "missed hint " << printReg(Hint, TRI) << '\n'); in tryAssign()
795 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << " is available at cost " in tryAssign()
825 << printReg(PrevReg, TRI) << " to " in canReassign()
826 << printReg(PhysReg, TRI) << '\n'); in canReassign()
1045 LLVM_DEBUG(dbgs() << "evicting " << printReg(PhysReg, TRI) in evictInterference()
1139 dbgs() << printReg(PhysReg, TRI) << " would clobber CSR " in tryEvict()
1140 << printReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI) in tryEvict()
1874 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tno positive bundles\n"); in calculateRegionSplitCost()
1877 LLVM_DEBUG(dbgs() << printReg(PhysReg, TRI) << "\tstatic = "; in calculateRegionSplitCost()
1885 << printReg(GlobalCand[BestCand].PhysReg, TRI) << '\n'; in calculateRegionSplitCost()
[all …]
DTargetRegisterInfo.cpp73 dbgs() << "Error: Super register " << printReg(*SR, this) in checkAllSuperRegsMarked()
74 << " of reserved register " << printReg(Reg, this) in checkAllSuperRegsMarked()
89 Printable printReg(unsigned Reg, const TargetRegisterInfo *TRI, in printReg() function
510 dbgs() << printReg(Reg, TRI, SubRegIndex) << "\n"; in dumpReg()
DRegisterCoalescer.cpp573 LLVM_DEBUG(dbgs() << "Extending: " << printReg(IntB.reg, TRI)); in adjustCopiesBackFrom()
1703 << printReg(CP.getSrcReg(), TRI) << " with " in joinCopy()
1704 << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n'); in joinCopy()
1725 dbgs() << printReg(CP.getDstReg()) << " in " in joinCopy()
1727 << printReg(CP.getSrcReg()) << " in " in joinCopy()
1730 dbgs() << printReg(CP.getSrcReg(), TRI) << " in " in joinCopy()
1731 << printReg(CP.getDstReg(), TRI, CP.getSrcIdx()) << '\n'; in joinCopy()
1822 dbgs() << "\tSuccess: " << printReg(CP.getSrcReg(), TRI, CP.getSrcIdx()) in joinCopy()
1823 << " -> " << printReg(CP.getDstReg(), TRI, CP.getDstIdx()) << '\n'; in joinCopy()
1826 dbgs() << printReg(CP.getDstReg(), TRI); in joinCopy()
[all …]
DStackMaps.cpp196 OS << printReg(Loc.Reg, TRI); in print()
203 OS << printReg(Loc.Reg, TRI); in print()
212 OS << printReg(Loc.Reg, TRI); in print()
236 OS << printReg(LO.Reg, TRI); in print()
DRegisterScavenging.cpp291 LLVM_DEBUG(dbgs() << "Scavenger found unused reg: " << printReg(Reg, TRI) in FindUnusedReg()
564 LLVM_DEBUG(dbgs() << "Scavenged register: " << printReg(SReg, TRI) << "\n"); in scavengeRegister()
572 << printReg(SReg, TRI) << "\n"); in scavengeRegister()
602 LLVM_DEBUG(dbgs() << "Scavenged register with spill: " << printReg(Reg, TRI) in scavengeRegisterBackwards()
605 LLVM_DEBUG(dbgs() << "Scavenged free register: " << printReg(Reg, TRI) in scavengeRegisterBackwards()
DMachineRegisterInfo.cpp226 errs() << printReg(Reg, getTargetRegisterInfo()) in verifyUseList()
235 errs() << printReg(Reg, getTargetRegisterInfo()) in verifyUseList()
241 errs() << printReg(Reg, getTargetRegisterInfo()) in verifyUseList()
247 errs() << printReg(Reg, getTargetRegisterInfo()) in verifyUseList()
DRenameIndependentSubregs.cpp137 LLVM_DEBUG(dbgs() << printReg(Reg) << ": Found " << Classes.getNumClasses() in INITIALIZE_PASS_DEPENDENCY()
139 LLVM_DEBUG(dbgs() << printReg(Reg) << ": Splitting into newly created:"); in INITIALIZE_PASS_DEPENDENCY()
145 LLVM_DEBUG(dbgs() << ' ' << printReg(NewVReg)); in INITIALIZE_PASS_DEPENDENCY()
DAllocationOrder.cpp46 dbgs() << ' ' << printReg(Hints[I], TRI); in AllocationOrder()
DRegisterUsageInfo.cpp98 OS << printReg(PReg, TRI) << " "; in print()
DCriticalAntiDepBreaker.cpp469 LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI)); in BreakAntiDependencies()
649 << printReg(AntiDepReg, TRI) << " with " in BreakAntiDependencies()
651 << " using " << printReg(NewReg, TRI) << "!\n"); in BreakAntiDependencies()
DVirtRegMap.cpp144 OS << '[' << printReg(Reg, TRI) << " -> " in print()
145 << printReg(Virt2PhysMap[Reg], TRI) << "] " in print()
153 OS << '[' << printReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg] in print()
/external/llvm/lib/CodeGen/
DMIRPrinter.cpp149 static void printReg(unsigned Reg, raw_ostream &OS, in printReg() function
162 static void printReg(unsigned Reg, yaml::StringValue &Dest, in printReg() function
165 printReg(Reg, OS, TRI); in printReg()
226 printReg(PreferredReg, VReg.PreferredRegister, TRI); in convert()
233 printReg(I->first, LiveIn.Register, TRI); in convert()
235 printReg(I->second, LiveIn.VirtualRegister, TRI); in convert()
247 printReg(I, Reg, TRI); in convert()
335 printReg(CSInfo.getReg(), Reg, TRI); in convertStackObjects()
494 printReg(LI.PhysReg, OS, TRI); in print()
773 printReg(Op.getReg(), OS, TRI); in print()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64A57FPLoadBalancing.cpp545 LLVM_DEBUG(dbgs() << " - Scavenged register: " << printReg(Reg, TRI) << "\n"); in colorChain()
619 << printReg(DestReg, TRI) << " at " << *MI); in scanInstruction()
639 << printReg(AccumReg, TRI) << " in MI " << *MI); in scanInstruction()
665 << printReg(DestReg, TRI) << "\n"); in scanInstruction()
693 LLVM_DEBUG(dbgs() << "Kill seen for chain " << printReg(MO.getReg(), TRI) in maybeKillChain()
705 << printReg(I->first, TRI) << "\n"); in maybeKillChain()
DAArch64PBQPRegAlloc.cpp250 LLVM_DEBUG(dbgs() << "Moving acc chain from " << printReg(Ra, TRI) in addInterChainConstraint()
251 << " to " << printReg(Rd, TRI) << '\n';); in addInterChainConstraint()
256 LLVM_DEBUG(dbgs() << "Creating new acc chain for " << printReg(Rd, TRI) in addInterChainConstraint()
343 LLVM_DEBUG(dbgs() << "Killing chain " << printReg(r, TRI) << " at "; in apply()
DAArch64FrameLowering.cpp1290 LLVM_DEBUG(dbgs() << "CSR spill: (" << printReg(Reg1, TRI); in spillCalleeSavedRegisters()
1291 if (RPI.isPaired()) dbgs() << ", " << printReg(Reg2, TRI); in spillCalleeSavedRegisters()
1351 LLVM_DEBUG(dbgs() << "CSR restore: (" << printReg(Reg1, TRI); in restoreCalleeSavedRegisters()
1352 if (RPI.isPaired()) dbgs() << ", " << printReg(Reg2, TRI); in restoreCalleeSavedRegisters()
1467 << ' ' << printReg(Reg, RegInfo); in determineCalleeSaves()
1491 LLVM_DEBUG(dbgs() << "Spilling " << printReg(UnspilledCSGPR, RegInfo) in determineCalleeSaves()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonGenInsert.cpp190 OS << ' ' << printReg(R, P.TRI); in operator <<()
431 OS << printReg(*I, P.TRI); in operator <<()
484 OS << '(' << printReg(SrcR, P.TRI) << ',' << printReg(InsR, P.TRI) in operator <<()
585 dbgs() << " " << printReg(I->first, HRI) << ":\n"; in dump_map()
798 dbgs() << __func__ << ": " << printReg(VR, HRI) in findRecordInsertForms()
863 dbgs() << "Prefixes matching register " << printReg(VR, HRI) << "\n"; in findRecordInsertForms()
868 dbgs() << " (" << printReg(LL[i].first, HRI) << ",@" in findRecordInsertForms()
915 dbgs() << printReg(VR, HRI) << " = insert(" << printReg(SrcR, HRI) in findRecordInsertForms()
916 << ',' << printReg(InsR, HRI) << ",#" << L << ",#" in findRecordInsertForms()
1544 dbgs() << printReg(VR, HRI) << " -> " << Pos << "\n"; in runOnMachineFunction()
DHexagonGenPredicate.cpp77 return OS << printReg(PR.Reg.R, &PR.TRI, PR.Reg.S); in operator <<()
225 LLVM_DEBUG(dbgs() << __func__ << ": " << printReg(Reg.R, TRI, Reg.S) << "\n"); in processPredicateGPR()
230 LLVM_DEBUG(dbgs() << "Dead reg: " << printReg(Reg.R, TRI, Reg.S) << '\n'); in processPredicateGPR()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARC/
DARCRegisterInfo.cpp69 LLVM_DEBUG(dbgs() << "Scavenged register " << printReg(BaseReg, TRI) in ReplaceFrameIndex()
70 << " for FrameReg=" << printReg(FrameReg, TRI) in ReplaceFrameIndex()
DARCInstrInfo.cpp301 LLVM_DEBUG(dbgs() << "Created store reg=" << printReg(SrcReg, TRI) in storeRegToStackSlot()
328 LLVM_DEBUG(dbgs() << "Created load reg=" << printReg(DestReg, TRI) in loadRegFromStackSlot()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/
DRegisterBankInfo.cpp435 LLVM_DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr)); in applyDefaultMapping()
437 LLVM_DEBUG(dbgs() << " with " << printReg(NewReg, nullptr)); in applyDefaultMapping()
748 OS << '(' << printReg(getMI().getOperand(Idx).getReg(), TRI) << ", ["; in print()
754 OS << printReg(VReg, TRI); in print()

1234