| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.h | 64 void printVRegOperand(const MCInst *MI, unsigned OpNo,
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| D | AArch64InstPrinter.cpp | 1013 void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo, in printVRegOperand() function in AArch64InstPrinter
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.h | 69 void printVRegOperand(const MCInst *MI, unsigned OpNo,
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| D | AArch64InstPrinter.cpp | 878 void AArch64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo, in printVRegOperand() function in AArch64InstPrinter
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 461 def V64 : RegisterOperand<FPR64, "printVRegOperand"> {
465 def V128 : RegisterOperand<FPR128, "printVRegOperand"> {
470 def V128_lo : RegisterOperand<FPR128_lo, "printVRegOperand"> {
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 480 def V64 : RegisterOperand<FPR64, "printVRegOperand"> {
484 def V128 : RegisterOperand<FPR128, "printVRegOperand"> {
492 def V128_lo : RegisterOperand<FPR128_lo, "printVRegOperand"> {
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| /external/capstone/arch/AArch64/ |
| D | AArch64GenAsmWriter.inc | 5214 printVRegOperand(MI, 0, O);
5222 printVRegOperand(MI, 1, O);
5745 printVRegOperand(MI, 1, O);
5766 printVRegOperand(MI, 1, O);
5774 printVRegOperand(MI, 2, O);
5808 printVRegOperand(MI, 3, O);
5828 printVRegOperand(MI, 2, O);
5837 printVRegOperand(MI, 2, O);
5907 printVRegOperand(MI, 2, O);
5913 printVRegOperand(MI, 3, O);
[all …]
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| D | AArch64InstPrinter.c | 670 static void printVRegOperand(MCInst *MI, unsigned OpNo, SStream *O) in printVRegOperand() function
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmWriter.inc | 9885 printVRegOperand(MI, 0, STI, O);
9893 printVRegOperand(MI, 1, STI, O);
10464 printVRegOperand(MI, 1, STI, O);
10517 printVRegOperand(MI, 1, STI, O);
10525 printVRegOperand(MI, 2, STI, O);
10636 printVRegOperand(MI, 3, STI, O);
10663 printVRegOperand(MI, 2, STI, O);
10670 printVRegOperand(MI, 2, STI, O);
10799 printVRegOperand(MI, 2, STI, O);
10805 printVRegOperand(MI, 3, STI, O);
[all …]
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| D | AArch64GenAsmWriter1.inc | 10834 printVRegOperand(MI, 0, STI, O);
10842 printVRegOperand(MI, 1, STI, O);
11233 printVRegOperand(MI, 1, STI, O);
11242 printVRegOperand(MI, 1, STI, O);
11249 printVRegOperand(MI, 1, STI, O);
11256 printVRegOperand(MI, 2, STI, O);
11448 printVRegOperand(MI, 1, STI, O);
11456 printVRegOperand(MI, 2, STI, O);
11577 printVRegOperand(MI, 3, STI, O);
11728 printVRegOperand(MI, 2, STI, O);
[all …]
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