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/external/skqp/src/gpu/
DGrPipeline.cpp20 GrProcessorSet&& processors, in GrPipeline() argument
22 SkASSERT(processors.isFinalized()); in GrPipeline()
39 fXferProcessor = processors.refXferProcessor(); in GrPipeline()
51 fNumColorProcessors = processors.numColorFragmentProcessors(); in GrPipeline()
53 processors.numCoverageFragmentProcessors() + in GrPipeline()
57 for (int i = 0; i < processors.numColorFragmentProcessors(); ++i, ++currFPIdx) { in GrPipeline()
58 fFragmentProcessors[currFPIdx] = processors.detachColorFragmentProcessor(i); in GrPipeline()
63 for (int i = 0; i < processors.numCoverageFragmentProcessors(); ++i, ++currFPIdx) { in GrPipeline()
64 fFragmentProcessors[currFPIdx] = processors.detachCoverageFragmentProcessor(i); in GrPipeline()
DGrProcessorAnalysis.cpp14 const GrFragmentProcessor* const* processors, in GrColorFragmentProcessorAnalysis() argument
26 const GrFragmentProcessor* fp = processors[i]; in GrColorFragmentProcessorAnalysis()
/external/skia/src/gpu/
DGrPipeline.cpp20 GrProcessorSet&& processors, in GrPipeline() argument
22 SkASSERT(processors.isFinalized()); in GrPipeline()
39 fXferProcessor = processors.refXferProcessor(); in GrPipeline()
51 fNumColorProcessors = processors.numColorFragmentProcessors(); in GrPipeline()
53 processors.numCoverageFragmentProcessors() + in GrPipeline()
57 for (int i = 0; i < processors.numColorFragmentProcessors(); ++i, ++currFPIdx) { in GrPipeline()
58 fFragmentProcessors[currFPIdx] = processors.detachColorFragmentProcessor(i); in GrPipeline()
63 for (int i = 0; i < processors.numCoverageFragmentProcessors(); ++i, ++currFPIdx) { in GrPipeline()
64 fFragmentProcessors[currFPIdx] = processors.detachCoverageFragmentProcessor(i); in GrPipeline()
DGrProcessorAnalysis.cpp14 const GrFragmentProcessor* const* processors, in GrColorFragmentProcessorAnalysis() argument
26 const GrFragmentProcessor* fp = processors[i]; in GrColorFragmentProcessorAnalysis()
/external/squashfs-tools/squashfs-tools/
Drestore.c54 extern int processors;
96 for(i = 0; i < processors; i++) in restore_thrd()
98 for(i = 0; i < processors; i++) in restore_thrd()
108 for(i = 0; i < processors; i++) in restore_thrd()
110 for(i = 0; i < processors; i++) in restore_thrd()
129 for(i = 0; i < processors; i++) in restore_thrd()
131 for(i = 0; i < processors; i++) in restore_thrd()
/external/jarjar/src/main/com/tonicsystems/jarjar/
DMainProcessor.java49 List<JarProcessor> processors = new ArrayList<JarProcessor>(); in MainProcessor() local
51 processors.add(ManifestProcessor.getInstance()); in MainProcessor()
53 processors.add(kp); in MainProcessor()
54 processors.add(new ZapProcessor(zapList)); in MainProcessor()
55 …processors.add(new JarTransformerChain(new RemappingClassTransformer[]{ new RemappingClassTransfor… in MainProcessor()
56 processors.add(new ResourceProcessor(pr)); in MainProcessor()
57 chain = new JarProcessorChain(processors.toArray(new JarProcessor[processors.size()])); in MainProcessor()
/external/turbine/java/com/google/turbine/options/
DTurbineOptions.java36 private final ImmutableSet<String> processors; field in TurbineOptions
56 ImmutableSet<String> processors, in TurbineOptions() argument
74 this.processors = checkNotNull(processors, "processors must not be null"); in TurbineOptions()
135 public ImmutableSet<String> processors() { in processors() method in TurbineOptions
136 return processors; in processors()
204 private final ImmutableSet.Builder<String> processors = ImmutableSet.builder(); field in TurbineOptions.Builder
228 processors.build(), in build()
276 public Builder addProcessors(Iterable<String> processors) { in addProcessors() argument
277 this.processors.addAll(processors); in addProcessors()
/external/icu/tools/srcgen/src/main/java/com/android/icu4j/srcgen/
DIcu4jTransform.java35 import com.google.currysrc.processors.AddAnnotation;
36 import com.google.currysrc.processors.AddDefaultConstructor;
37 import com.google.currysrc.processors.HidePublicClasses;
38 import com.google.currysrc.processors.InsertHeader;
39 import com.google.currysrc.processors.ModifyQualifiedNames;
40 import com.google.currysrc.processors.ModifyStringLiterals;
41 import com.google.currysrc.processors.RemoveJavaDocTags;
42 import com.google.currysrc.processors.RenamePackage;
43 import com.google.currysrc.processors.ReplaceTextCommentScanner;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARM.td225 // Some processors benefit from using NEON instructions for scalar
233 // On some processors, VLDn instructions that access unaligned data take one
239 // Some processors have a nonpipelined VFP coprocessor.
244 // Some processors have FP multiply-accumulate instructions that don't
262 /// processors.
279 // Some processors perform return stack prediction. CodeGen should avoid issue
285 // Some processors have no branch predictor, which changes the expected cost of
448 "Cortex-A5 ARM processors", []>;
450 "Cortex-A7 ARM processors", []>;
452 "Cortex-A8 ARM processors", []>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64.td252 "Cortex-A35 ARM processors", [
261 "Cortex-A53 ARM processors", [
275 "Cortex-A55 ARM processors", [
288 "Cortex-A57 ARM processors", [
303 "Cortex-A72 ARM processors", [
313 "Cortex-A73 ARM processors", [
323 "Cortex-A75 ARM processors", [
354 "Samsung Exynos-M1 processors",
369 "Samsung Exynos-M2 processors",
383 "Samsung Exynos-M3 processors",
[all …]
/external/llvm/lib/Target/ARM/
DARM.td166 // Some processors benefit from using NEON instructions for scalar
173 // On some processors, VLDn instructions that access unaligned data take one
179 // Some processors have a nonpipelined VFP coprocessor.
184 // Some processors have FP multiply-accumulate instructions that don't
202 /// processors.
211 // Some processors perform return stack prediction. CodeGen should avoid issue
315 "Cortex-A5 ARM processors", []>;
317 "Cortex-A7 ARM processors", []>;
319 "Cortex-A8 ARM processors", []>;
321 "Cortex-A9 ARM processors", []>;
[all …]
/external/u-boot/board/freescale/mx6ullevk/
DREADME35 processors/arm-processors/i.mx-applications-processors/i.mx-6-processors/ \
/external/epid-sdk/ext/ipp/sources/include/
Dippres.gen129 …R) Integrated Performance Primitives. " IPP_LIB_LONGNAME() ". For Intel(R) Pentium(R) processors\0"
135 …rimitives. " IPP_LIB_LONGNAME() ". For Intel(R) 64 Instruction Set Architecture (ISA) processors\0"
141 …R) Integrated Performance Primitives. " IPP_LIB_LONGNAME() ". For Intel(R) Itanium(R) processors\0"
153 …tegrated Performance Primitives. " IPP_LIB_LONGNAME() ". Optimized for processors with Streaming S…
159 …tegrated Performance Primitives. " IPP_LIB_LONGNAME() ". Optimized for processors with Streaming S…
165 …tegrated Performance Primitives. " IPP_LIB_LONGNAME() ". Optimized for processors with Streaming S…
171 …tegrated Performance Primitives. " IPP_LIB_LONGNAME() ". Optimized for processors with Supplementa…
177 …tegrated Performance Primitives. " IPP_LIB_LONGNAME() ". Optimized for processors with Streaming S…
183 …tegrated Performance Primitives. " IPP_LIB_LONGNAME() ". Optimized for processors with Advanced Ve…
189 …tegrated Performance Primitives. " IPP_LIB_LONGNAME() ". Optimized for processors with Advanced Ve…
[all …]
/external/u-boot/doc/
DREADME.ARC12 The DesignWare ARC processors are also extendable, allowing designers to add
15 Synopsys' ARC processors have been used by over 170 customers worldwide who
18 All DesignWare ARC processors utilize a 16-/32-bit ISA that provides excellent
27 https://github.com/foss-for-synopsys-dwc-arc-processors/toolchain/releases
DREADME.arm6432 4. Spin-table is used to wake up secondary processors. One location
34 for secondary processors. It must be ensured that the location is
38 of secondary processors to it and send event to wakeup secondary
39 processors.
/external/icu/tools/srcgen/currysrc/src/main/java/com/google/currysrc/aosp/
DRepackagingTransform.java31 import com.google.currysrc.processors.AddAnnotation;
32 import com.google.currysrc.processors.AddDefaultConstructor;
33 import com.google.currysrc.processors.HidePublicClasses;
34 import com.google.currysrc.processors.InsertHeader;
35 import com.google.currysrc.processors.ModifyQualifiedNames;
36 import com.google.currysrc.processors.ModifyStringLiterals;
37 import com.google.currysrc.processors.RenamePackage;
DAnnotations.java20 import com.google.currysrc.processors.AddAnnotation;
21 import com.google.currysrc.processors.AnnotationInfo.AnnotationClass;
/external/llvm/lib/Target/AArch64/
DAArch64.td151 "Cortex-A35 ARM processors", [
160 "Cortex-A53 ARM processors", [
173 "Cortex-A57 ARM processors", [
187 "Cortex-A72 ARM processors", [
196 "Cortex-A73 ARM processors", [
219 "Samsung Exynos-M1 processors", [
232 "Qualcomm Kryo processors", [
246 "Broadcom Vulcan processors", [
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DLeonFeatures.td15 // UMAC and SMAC support for LEON3 and LEON4 processors.
23 "Enable UMAC and SMAC for LEON3 and LEON4 processors"
37 "Enable CASA instruction for LEON3 and LEON4 processors"
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86.td64 // SSE1+ processors support them.
262 // On some processors, instructions that implicitly take two memory operands are
287 // On recent X86 (port bound) processors, its preferable to combine to a single shuffle
293 // On some X86 processors, there is no performance hazard to writing only the
328 // Sandy Bridge and newer processors can use SHLD with the same source on both
336 // Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka
346 // Sandy Bridge and newer processors have many instructions that can be
354 // generate Gathers on all AVX2 processors. But the overhead on HSW is high.
410 // X86 processors supported.
424 "Intel Atom processors">;
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/external/u-boot/board/ti/ks2_evm/
DREADME88 http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Getting_Started#
92 K2HK http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup
93 K2E http://processors.wiki.ti.com/index.php/EVMK2E_Hardware_Setup
94 K2L http://processors.wiki.ti.com/index.php/TCIEVMK2L_Hardware_Setup
95 K2G http://processors.wiki.ti.com/index.php/66AK2G02_GP_EVM_Hardware_Setup
102 configuration as instructed at http://processors.wiki.ti.com/index.php/
150 http://processors.wiki.ti.com/index.php/*_Hardware_Setup.
170 http://processors.wiki.ti.com/index.php/*_Hardware_Setup.
190 http://processors.wiki.ti.com/index.php/66AK2G02_GP_EVM_Hardware_Setup
/external/skqp/gn/
Dcompile_processors.py14 processors = sys.argv[3:] variable
15 for p in processors:
/external/skia/gn/
Dcompile_processors.py14 processors = sys.argv[3:] variable
15 for p in processors:
/external/markdown/docs/
Drelease-2.0.txt28 * The various processors and patterns are now stored with OrderedDicts rather
29 than lists. Any code adding processors and/or patterns into Python-Markdown
31 * The various types of processors available have been either combined, added,
32 or removed. Ensure that your processors match the currently supported types.
/external/tensorflow/tensorflow/lite/nnapi/
DREADME.md9 processors, including dedicated neural network hardware, graphics processing
10 units (GPUs), and digital signal processors (DSPs).

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