/external/llvm/test/CodeGen/ARM/ |
D | thumb-big-stack.ll | 145 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q… 147 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q… 149 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q… 151 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q… 153 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q… 155 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q… 157 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q… 159 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q… 161 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q… 163 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q… [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
D | thumb-big-stack.ll | 145 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q… 147 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q… 149 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q… 151 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q… 153 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q… 155 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q… 157 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q… 159 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q… 161 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q… 163 …tail call void asm sideeffect "", "~{q0}{q1}{q2}{q3}{q4}{q5}{q6}{q7}{q8}{q9}{q10}{q11}{q12}{q13}{q… [all …]
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/external/capstone/suite/MC/ARM/ |
D | neon-bitwise-encoding.s.cs | 92 0x5a,0xc1,0x0c,0xf2 = vand q6, q6, q5 93 0x5a,0xc1,0x0c,0xf2 = vand q6, q6, q5 97 0x5a,0xc1,0x0c,0xf3 = veor q6, q6, q5 98 0x5a,0xc1,0x0c,0xf3 = veor q6, q6, q5 102 0x5a,0xc1,0x0c,0xf3 = veor q6, q6, q5 103 0x5a,0xc1,0x0c,0xf3 = veor q6, q6, q5 107 0x4a,0xa2,0xb5,0xf3 = vclt.s16 q5, q5, #0 109 0x56,0xa8,0x1a,0xf3 = vceq.i16 q5, q5, q3 111 0x46,0xa3,0x1a,0xf2 = vcgt.s16 q5, q5, q3 113 0x56,0xa3,0x1a,0xf2 = vcge.s16 q5, q5, q3 [all …]
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D | neon-shiftaccum-encoding.s.cs | 8 0x5a,0x21,0xe0,0xf2 = vsra.s32 q9, q5, #32 17 0xda,0x81,0xa7,0xf3 = vsra.u64 q4, q5, #25 24 0x5a,0xa1,0xa0,0xf2 = vsra.s32 q5, q5, #32 33 0xda,0xa1,0xa7,0xf3 = vsra.u64 q5, q5, #25 45 0xda,0x83,0x80,0xf2 = vrsra.s64 q4, q5, #64 46 0x5c,0xa3,0x88,0xf3 = vrsra.u8 q5, q6, #8 61 0xda,0xa3,0x80,0xf2 = vrsra.s64 q5, q5, #64 73 0xda,0x85,0xbf,0xf3 = vsli.64 q4, q5, #63 79 0x54,0xa4,0x90,0xf3 = vsri.16 q5, q2, #16 89 0xda,0xa5,0xbf,0xf3 = vsli.64 q5, q5, #63
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D | neont2-shiftaccum-encoding.s.cs | 8 0xe0,0xef,0x5a,0x21 = vsra.s32 q9, q5, #32 17 0xa7,0xff,0xda,0x81 = vsra.u64 q4, q5, #25 24 0xa0,0xef,0x5a,0xa1 = vsra.s32 q5, q5, #32 33 0xa7,0xff,0xda,0xa1 = vsra.u64 q5, q5, #25 45 0x80,0xef,0xda,0x83 = vrsra.s64 q4, q5, #64 46 0x88,0xff,0x5c,0xa3 = vrsra.u8 q5, q6, #8 61 0x80,0xef,0xda,0xa3 = vrsra.s64 q5, q5, #64 73 0xbf,0xff,0xda,0x85 = vsli.64 q4, q5, #63 79 0x90,0xff,0x54,0xa4 = vsri.16 q5, q2, #16 89 0xbf,0xff,0xda,0xa5 = vsli.64 q5, q5, #63
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D | neon-shift-encoding.s.cs | 57 0xda,0x81,0x81,0xf2 = vsra.s64 q4, q5, #63 63 0x5a,0xa1,0x91,0xf2 = vsra.s16 q5, q5, #15 73 0xda,0x81,0x81,0xf3 = vsra.u64 q4, q5, #63 79 0x5a,0xa1,0x91,0xf3 = vsra.u16 q5, q5, #15 89 0xda,0x84,0x81,0xf3 = vsri.64 q4, q5, #63 95 0x5a,0xa4,0x91,0xf3 = vsri.16 q5, q5, #15 105 0xda,0x85,0xbf,0xf3 = vsli.64 q4, q5, #63 111 0x5a,0xa5,0x9f,0xf3 = vsli.16 q5, q5, #15 167 0x48,0x84,0x0a,0xf2 = vshl.s8 q4, q4, q5 168 0x48,0x84,0x1a,0xf2 = vshl.s16 q4, q4, q5 [all …]
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D | neon-minmax-encoding.s.cs | 17 0x4c,0x86,0x1a,0xf2 = vmax.s16 q4, q5, q6 22 0x42,0x2f,0x4a,0xf2 = vmax.f32 q9, q5, q1 24 0x4c,0xa6,0x1a,0xf2 = vmax.s16 q5, q5, q6 27 0x4a,0x86,0x18,0xf3 = vmax.u16 q4, q4, q5 45 0x5c,0x86,0x1a,0xf2 = vmin.s16 q4, q5, q6 50 0x42,0x2f,0x6a,0xf2 = vmin.f32 q9, q5, q1 52 0x5c,0xa6,0x1a,0xf2 = vmin.s16 q5, q5, q6 55 0x5a,0x86,0x18,0xf3 = vmin.u16 q4, q4, q5
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D | neont2-minmax-encoding.s.cs | 17 0x1a,0xef,0x4c,0x86 = vmax.s16 q4, q5, q6 22 0x4a,0xef,0x42,0x2f = vmax.f32 q9, q5, q1 24 0x1a,0xef,0x4c,0xa6 = vmax.s16 q5, q5, q6 27 0x18,0xff,0x4a,0x86 = vmax.u16 q4, q4, q5 45 0x1a,0xef,0x5c,0x86 = vmin.s16 q4, q5, q6 50 0x6a,0xef,0x42,0x2f = vmin.f32 q9, q5, q1 52 0x1a,0xef,0x5c,0xa6 = vmin.s16 q5, q5, q6 55 0x18,0xff,0x5a,0x86 = vmin.u16 q4, q4, q5
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/external/libavc/common/arm/ |
D | ih264_inter_pred_luma_horz_qpel_vert_qpel_a9q.s | 146 vld1.32 {q5}, [r7], r2 @ Vector load from src[5_0] 248 vaddl.u8 q5, d0, d5 249 vmlal.u8 q5, d2, d30 250 vmlal.u8 q5, d3, d30 251 vmlsl.u8 q5, d1, d31 252 vmlsl.u8 q5, d4, d31 259 vqrshrun.s16 d26, q5, #5 261 vaddl.u8 q5, d12, d17 262 vmlal.u8 q5, d14, d30 263 vmlal.u8 q5, d15, d30 [all …]
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/external/libvpx/libvpx/vp8/common/arm/neon/ |
D | idct_blk_neon.c | 71 int16x8_t q0, q1, q2, q3, q4, q5, q6, q7, q8, q9, q10, q11; in idct_dequant_full_2x_neon() local 94 q5 = vld1q_s16(q); in idct_dequant_full_2x_neon() 119 q5 = vmulq_s16(q5, q1); in idct_dequant_full_2x_neon() 131 dLow1 = vget_low_s16(q5); in idct_dequant_full_2x_neon() 132 dHigh1 = vget_high_s16(q5); in idct_dequant_full_2x_neon() 134 q5 = vcombine_s16(dHigh0, dHigh1); in idct_dequant_full_2x_neon() 137 q7 = vqdmulhq_n_s16(q5, sinpi8sqrt2); in idct_dequant_full_2x_neon() 139 q9 = vqdmulhq_n_s16(q5, cospi8sqrt2minus1); in idct_dequant_full_2x_neon() 148 q5 = vqaddq_s16(q5, q9); in idct_dequant_full_2x_neon() 150 q2 = vqsubq_s16(q6, q5); in idct_dequant_full_2x_neon() [all …]
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D | vp8_loopfilter_neon.c | 20 uint8x16_t q5, // p1 in vp8_loop_filter_neon() argument 37 q12u8 = vabdq_u8(q4, q5); in vp8_loop_filter_neon() 38 q13u8 = vabdq_u8(q5, q6); in vp8_loop_filter_neon() 55 q2u8 = vabdq_u8(q5, q8); in vp8_loop_filter_neon() 66 q5 = veorq_u8(q5, q10); in vp8_loop_filter_neon() 80 q1s8 = vqsubq_s8(vreinterpretq_s8_u8(q5), vreinterpretq_s8_u8(q8)); in vp8_loop_filter_neon() 114 q13s8 = vqaddq_s8(vreinterpretq_s8_u8(q5), q1s8); in vp8_loop_filter_neon() 130 uint8x16_t q5, q6, q7, q8, q9, q10; in vp8_loop_filter_horizontal_edge_y_neon() local 141 q5 = vld1q_u8(src); in vp8_loop_filter_horizontal_edge_y_neon() 153 vp8_loop_filter_neon(qblimit, qlimit, qthresh, q3, q4, q5, q6, q7, q8, q9, in vp8_loop_filter_horizontal_edge_y_neon() [all …]
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D | mbloopfilter_neon.c | 19 uint8x16_t q5, // p1 in vp8_mbloop_filter_neon() argument 39 q12u8 = vabdq_u8(q4, q5); in vp8_mbloop_filter_neon() 40 q13u8 = vabdq_u8(q5, q6); in vp8_mbloop_filter_neon() 59 q1u8 = vabdq_u8(q5, q8); in vp8_mbloop_filter_neon() 69 q5 = veorq_u8(q5, q0u8); in vp8_mbloop_filter_neon() 83 q1s8 = vqsubq_s8(vreinterpretq_s8_u8(q5), vreinterpretq_s8_u8(q8)); in vp8_mbloop_filter_neon() 139 q12s8 = vqaddq_s8(vreinterpretq_s8_u8(q5), q12s8); in vp8_mbloop_filter_neon() 158 uint8x16_t q5, q6, q7, q8, q9, q10; in vp8_mbloop_filter_horizontal_edge_y_neon() local 170 q5 = vld1q_u8(src); in vp8_mbloop_filter_horizontal_edge_y_neon() 182 vp8_mbloop_filter_neon(qblimit, qlimit, qthresh, q3, q4, q5, q6, q7, q8, q9, in vp8_mbloop_filter_horizontal_edge_y_neon() [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
D | neont2-shiftaccum-encoding.s | 11 vsra.s32 q9, q5, #32 20 vsra.u64 q4, q5, #25 29 vsra.s32 q5, #32 38 vsra.u64 q5, #25 46 @ CHECK: vsra.s32 q9, q5, #32 @ encoding: [0xe0,0xef,0x5a,0x21] 55 @ CHECK: vsra.u64 q4, q5, #25 @ encoding: [0xa7,0xff,0xda,0x81] 63 @ CHECK: vsra.s32 q5, q5, #32 @ encoding: [0xa0,0xef,0x5a,0xa1] 72 @ CHECK: vsra.u64 q5, q5, #25 @ encoding: [0xa7,0xff,0xda,0xa1] 86 vrsra.s64 q4, q5, #64 87 vrsra.u8 q5, q6, #8 [all …]
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D | neon-shiftaccum-encoding.s | 9 vsra.s32 q9, q5, #32 18 vsra.u64 q4, q5, #25 27 vsra.s32 q5, #32 36 vsra.u64 q5, #25 44 @ CHECK: vsra.s32 q9, q5, #32 @ encoding: [0x5a,0x21,0xe0,0xf2] 53 @ CHECK: vsra.u64 q4, q5, #25 @ encoding: [0xda,0x81,0xa7,0xf3] 61 @ CHECK: vsra.s32 q5, q5, #32 @ encoding: [0x5a,0xa1,0xa0,0xf2] 70 @ CHECK: vsra.u64 q5, q5, #25 @ encoding: [0xda,0xa1,0xa7,0xf3] 83 vrsra.s64 q4, q5, #64 84 vrsra.u8 q5, q6, #8 [all …]
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D | neont2-minmax-encoding.s | 22 vmax.s16 q4, q5, q6 27 vmax.f32 q9, q5, q1 30 vmax.s16 q5, q6 33 vmax.u16 q4, q5 52 @ CHECK: vmax.s16 q4, q5, q6 @ encoding: [0x1a,0xef,0x4c,0x86] 57 @ CHECK: vmax.f32 q9, q5, q1 @ encoding: [0x4a,0xef,0x42,0x2f] 59 @ CHECK: vmax.s16 q5, q5, q6 @ encoding: [0x1a,0xef,0x4c,0xa6] 62 @ CHECK: vmax.u16 q4, q4, q5 @ encoding: [0x18,0xff,0x4a,0x86] 84 vmin.s16 q4, q5, q6 89 vmin.f32 q9, q5, q1 [all …]
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D | neon-minmax-encoding.s | 20 vmax.s16 q4, q5, q6 25 vmax.f32 q9, q5, q1 28 vmax.s16 q5, q6 31 vmax.u16 q4, q5 50 @ CHECK: vmax.s16 q4, q5, q6 @ encoding: [0x4c,0x86,0x1a,0xf2] 55 @ CHECK: vmax.f32 q9, q5, q1 @ encoding: [0x42,0x2f,0x4a,0xf2] 57 @ CHECK: vmax.s16 q5, q5, q6 @ encoding: [0x4c,0xa6,0x1a,0xf2] 60 @ CHECK: vmax.u16 q4, q4, q5 @ encoding: [0x4a,0x86,0x18,0xf3] 82 vmin.s16 q4, q5, q6 87 vmin.f32 q9, q5, q1 [all …]
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D | neon-shift-encoding.s | 116 vsra.s64 q4, q5, #63 123 vsra.s16 q5, #15 134 @ CHECK: vsra.s64 q4, q5, #63 @ encoding: [0xda,0x81,0x81,0xf2] 140 @ CHECK: vsra.s16 q5, q5, #15 @ encoding: [0x5a,0xa1,0x91,0xf2] 152 vsra.u64 q4, q5, #63 159 vsra.u16 q5, #15 170 @ CHECK: vsra.u64 q4, q5, #63 @ encoding: [0xda,0x81,0x81,0xf3] 176 @ CHECK: vsra.u16 q5, q5, #15 @ encoding: [0x5a,0xa1,0x91,0xf3] 188 vsri.64 q4, q5, #63 195 vsri.16 q5, #15 [all …]
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/external/llvm/test/MC/ARM/ |
D | neon-shiftaccum-encoding.s | 9 vsra.s32 q9, q5, #32 18 vsra.u64 q4, q5, #25 27 vsra.s32 q5, #32 36 vsra.u64 q5, #25 44 @ CHECK: vsra.s32 q9, q5, #32 @ encoding: [0x5a,0x21,0xe0,0xf2] 53 @ CHECK: vsra.u64 q4, q5, #25 @ encoding: [0xda,0x81,0xa7,0xf3] 61 @ CHECK: vsra.s32 q5, q5, #32 @ encoding: [0x5a,0xa1,0xa0,0xf2] 70 @ CHECK: vsra.u64 q5, q5, #25 @ encoding: [0xda,0xa1,0xa7,0xf3] 83 vrsra.s64 q4, q5, #64 84 vrsra.u8 q5, q6, #8 [all …]
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D | neont2-shiftaccum-encoding.s | 11 vsra.s32 q9, q5, #32 20 vsra.u64 q4, q5, #25 29 vsra.s32 q5, #32 38 vsra.u64 q5, #25 46 @ CHECK: vsra.s32 q9, q5, #32 @ encoding: [0xe0,0xef,0x5a,0x21] 55 @ CHECK: vsra.u64 q4, q5, #25 @ encoding: [0xa7,0xff,0xda,0x81] 63 @ CHECK: vsra.s32 q5, q5, #32 @ encoding: [0xa0,0xef,0x5a,0xa1] 72 @ CHECK: vsra.u64 q5, q5, #25 @ encoding: [0xa7,0xff,0xda,0xa1] 86 vrsra.s64 q4, q5, #64 87 vrsra.u8 q5, q6, #8 [all …]
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D | neont2-minmax-encoding.s | 22 vmax.s16 q4, q5, q6 27 vmax.f32 q9, q5, q1 30 vmax.s16 q5, q6 33 vmax.u16 q4, q5 52 @ CHECK: vmax.s16 q4, q5, q6 @ encoding: [0x1a,0xef,0x4c,0x86] 57 @ CHECK: vmax.f32 q9, q5, q1 @ encoding: [0x4a,0xef,0x42,0x2f] 59 @ CHECK: vmax.s16 q5, q5, q6 @ encoding: [0x1a,0xef,0x4c,0xa6] 62 @ CHECK: vmax.u16 q4, q4, q5 @ encoding: [0x18,0xff,0x4a,0x86] 84 vmin.s16 q4, q5, q6 89 vmin.f32 q9, q5, q1 [all …]
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D | neon-minmax-encoding.s | 20 vmax.s16 q4, q5, q6 25 vmax.f32 q9, q5, q1 28 vmax.s16 q5, q6 31 vmax.u16 q4, q5 50 @ CHECK: vmax.s16 q4, q5, q6 @ encoding: [0x4c,0x86,0x1a,0xf2] 55 @ CHECK: vmax.f32 q9, q5, q1 @ encoding: [0x42,0x2f,0x4a,0xf2] 57 @ CHECK: vmax.s16 q5, q5, q6 @ encoding: [0x4c,0xa6,0x1a,0xf2] 60 @ CHECK: vmax.u16 q4, q4, q5 @ encoding: [0x4a,0x86,0x18,0xf3] 82 vmin.s16 q4, q5, q6 87 vmin.f32 q9, q5, q1 [all …]
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D | neon-shift-encoding.s | 116 vsra.s64 q4, q5, #63 123 vsra.s16 q5, #15 134 @ CHECK: vsra.s64 q4, q5, #63 @ encoding: [0xda,0x81,0x81,0xf2] 140 @ CHECK: vsra.s16 q5, q5, #15 @ encoding: [0x5a,0xa1,0x91,0xf2] 152 vsra.u64 q4, q5, #63 159 vsra.u16 q5, #15 170 @ CHECK: vsra.u64 q4, q5, #63 @ encoding: [0xda,0x81,0x81,0xf3] 176 @ CHECK: vsra.u16 q5, q5, #15 @ encoding: [0x5a,0xa1,0x91,0xf3] 188 vsri.64 q4, q5, #63 195 vsri.16 q5, #15 [all …]
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/external/libhevc/common/arm/ |
D | ihevc_inter_pred_luma_vert_w16inp_w16out.s | 179 vmull.s16 q5,d2,d23 @mul_res2 = vmull_u8(src_tmp3, coeffabs_1)@ 181 vmlal.s16 q5,d1,d22 @mul_res2 = vmlal_u8(mul_res2, src_tmp2, coeffabs_0)@ 183 vmlal.s16 q5,d3,d24 @mul_res2 = vmlal_u8(mul_res2, src_tmp4, coeffabs_2)@ 185 vmlal.s16 q5,d4,d25 @mul_res2 = vmlal_u8(mul_res2, src_tmp1, coeffabs_3)@ 187 vmlal.s16 q5,d5,d26 @mul_res2 = vmlal_u8(mul_res2, src_tmp2, coeffabs_4)@ 189 vmlal.s16 q5,d6,d27 @mul_res2 = vmlal_u8(mul_res2, src_tmp3, coeffabs_5)@ 190 vmlal.s16 q5,d7,d28 @mul_res2 = vmlal_u8(mul_res2, src_tmp4, coeffabs_6)@ 191 vmlal.s16 q5,d16,d29 @mul_res2 = vmlal_u8(mul_res2, src_tmp1, coeffabs_7)@ 206 vsub.s32 q5, q5, q15 226 vshrn.s32 d10, q5, #6 [all …]
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D | ihevc_inter_pred_filters_luma_vert_w16inp.s | 169 vmull.s16 q5,d2,d23 @mul_res2 = vmull_u8(src_tmp3, coeffabs_1)@ 171 vmlal.s16 q5,d1,d22 @mul_res2 = vmlal_u8(mul_res2, src_tmp2, coeffabs_0)@ 173 vmlal.s16 q5,d3,d24 @mul_res2 = vmlal_u8(mul_res2, src_tmp4, coeffabs_2)@ 175 vmlal.s16 q5,d4,d25 @mul_res2 = vmlal_u8(mul_res2, src_tmp1, coeffabs_3)@ 177 vmlal.s16 q5,d5,d26 @mul_res2 = vmlal_u8(mul_res2, src_tmp2, coeffabs_4)@ 179 vmlal.s16 q5,d6,d27 @mul_res2 = vmlal_u8(mul_res2, src_tmp3, coeffabs_5)@ 180 vmlal.s16 q5,d7,d28 @mul_res2 = vmlal_u8(mul_res2, src_tmp4, coeffabs_6)@ 181 vmlal.s16 q5,d16,d29 @mul_res2 = vmlal_u8(mul_res2, src_tmp1, coeffabs_7)@ 196 vqshrn.s32 d10, q5, #6 215 vqrshrun.s16 d10,q5,#6 @sto_res = vqmovun_s16(sto_res_tmp)@ [all …]
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/external/boringssl/src/crypto/curve25519/asm/ |
D | x25519-asm-arm.S | 40 vpush {q4,q5,q6,q7} 109 vshr.u64 q5,q5,#26 122 vand q5,q5,q3 132 vadd.i64 q5,q5,q12 134 vadd.i64 q14,q5,q0 146 vsub.i64 q5,q5,q12 195 vadd.i64 q5,q5,q1 256 veor q6,q4,q5 268 veor q5,q5,q6 306 vadd.i32 q2,q5,q7 [all …]
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