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/external/capstone/suite/MC/SystemZ/
Dinsn-good-z196.s.cs2 0xec,0x00,0x80,0x00,0x00,0xd9 = aghik %r0, %r0, -32768
3 0xec,0x00,0xff,0xff,0x00,0xd9 = aghik %r0, %r0, -1
4 0xec,0x00,0x00,0x00,0x00,0xd9 = aghik %r0, %r0, 0
5 0xec,0x00,0x00,0x01,0x00,0xd9 = aghik %r0, %r0, 1
6 0xec,0x00,0x7f,0xff,0x00,0xd9 = aghik %r0, %r0, 32767
7 0xec,0x0f,0x00,0x00,0x00,0xd9 = aghik %r0, %r15, 0
8 0xec,0xf0,0x00,0x00,0x00,0xd9 = aghik %r15, %r0, 0
10 0xb9,0xe8,0x00,0x00 = agrk %r0, %r0, %r0
11 0xb9,0xe8,0xf0,0x00 = agrk %r0, %r0, %r15
12 0xb9,0xe8,0x00,0x0f = agrk %r0, %r15, %r0
[all …]
Dinsn-good.s.cs2 0x5a,0x00,0x00,0x00 = a %r0, 0
3 0x5a,0x00,0x0f,0xff = a %r0, 4095
4 0x5a,0x00,0x10,0x00 = a %r0, 0(%r1)
5 0x5a,0x00,0xf0,0x00 = a %r0, 0(%r15)
6 0x5a,0x01,0xff,0xff = a %r0, 4095(%r1,%r15)
7 0x5a,0x0f,0x1f,0xff = a %r0, 4095(%r15,%r1)
31 0xc2,0x09,0x80,0x00,0x00,0x00 = afi %r0, -2147483648
32 0xc2,0x09,0xff,0xff,0xff,0xff = afi %r0, -1
33 0xc2,0x09,0x00,0x00,0x00,0x00 = afi %r0, 0
34 0xc2,0x09,0x00,0x00,0x00,0x01 = afi %r0, 1
[all …]
/external/llvm/test/MC/SystemZ/
Dinsn-good-z196.s4 #CHECK: aghik %r0, %r0, -32768 # encoding: [0xec,0x00,0x80,0x00,0x00,0xd9]
5 #CHECK: aghik %r0, %r0, -1 # encoding: [0xec,0x00,0xff,0xff,0x00,0xd9]
6 #CHECK: aghik %r0, %r0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0xd9]
7 #CHECK: aghik %r0, %r0, 1 # encoding: [0xec,0x00,0x00,0x01,0x00,0xd9]
8 #CHECK: aghik %r0, %r0, 32767 # encoding: [0xec,0x00,0x7f,0xff,0x00,0xd9]
9 #CHECK: aghik %r0, %r15, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0xd9]
10 #CHECK: aghik %r15, %r0, 0 # encoding: [0xec,0xf0,0x00,0x00,0x00,0xd9]
13 aghik %r0, %r0, -32768
14 aghik %r0, %r0, -1
15 aghik %r0, %r0, 0
[all …]
Dinsn-bad-z196.s6 #CHECK: aghik %r0, %r1, -32769
8 #CHECK: aghik %r0, %r1, 32768
10 #CHECK: aghik %r0, %r1, foo
12 aghik %r0, %r1, -32769
13 aghik %r0, %r1, 32768
14 aghik %r0, %r1, foo
17 #CHECK: ahik %r0, %r1, -32769
19 #CHECK: ahik %r0, %r1, 32768
21 #CHECK: ahik %r0, %r1, foo
23 ahik %r0, %r1, -32769
[all …]
Dinsn-bad.s6 #CHECK: a %r0, -1
8 #CHECK: a %r0, 4096
10 a %r0, -1
11 a %r0, 4096
30 #CHECK: afi %r0, (-1 << 31) - 1
32 #CHECK: afi %r0, (1 << 31)
34 afi %r0, (-1 << 31) - 1
35 afi %r0, (1 << 31)
38 #CHECK: ag %r0, -524289
40 #CHECK: ag %r0, 524288
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/SystemZ/
Dinsn-good-z196.s19 #CHECK: aghik %r0, %r0, -32768 # encoding: [0xec,0x00,0x80,0x00,0x00,0xd9]
20 #CHECK: aghik %r0, %r0, -1 # encoding: [0xec,0x00,0xff,0xff,0x00,0xd9]
21 #CHECK: aghik %r0, %r0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0xd9]
22 #CHECK: aghik %r0, %r0, 1 # encoding: [0xec,0x00,0x00,0x01,0x00,0xd9]
23 #CHECK: aghik %r0, %r0, 32767 # encoding: [0xec,0x00,0x7f,0xff,0x00,0xd9]
24 #CHECK: aghik %r0, %r15, 0 # encoding: [0xec,0x0f,0x00,0x00,0x00,0xd9]
25 #CHECK: aghik %r15, %r0, 0 # encoding: [0xec,0xf0,0x00,0x00,0x00,0xd9]
28 aghik %r0, %r0, -32768
29 aghik %r0, %r0, -1
30 aghik %r0, %r0, 0
[all …]
Dinsn-bad-z196.s16 #CHECK: aghik %r0, %r1, -32769
18 #CHECK: aghik %r0, %r1, 32768
20 #CHECK: aghik %r0, %r1, foo
22 aghik %r0, %r1, -32769
23 aghik %r0, %r1, 32768
24 aghik %r0, %r1, foo
27 #CHECK: ahik %r0, %r1, -32769
29 #CHECK: ahik %r0, %r1, 32768
31 #CHECK: ahik %r0, %r1, foo
33 ahik %r0, %r1, -32769
[all …]
/external/libffi/src/arm/
Dtrampoline.S34 stmfd sp!, {r0-r3}
39 ldr r0, [pc, #-4092]
47 stmfd sp!, {r0-r3}
52 ldr r0, [pc, #-4092]
60 stmfd sp!, {r0-r3}
65 ldr r0, [pc, #-4092]
73 stmfd sp!, {r0-r3}
78 ldr r0, [pc, #-4092]
86 stmfd sp!, {r0-r3}
91 ldr r0, [pc, #-4092]
[all …]
/external/python/cpython2/Modules/_ctypes/libffi/src/arm/
Dtrampoline.S34 stmfd sp!, {r0-r3}
39 ldr r0, [pc, #-4092]
47 stmfd sp!, {r0-r3}
52 ldr r0, [pc, #-4092]
60 stmfd sp!, {r0-r3}
65 ldr r0, [pc, #-4092]
73 stmfd sp!, {r0-r3}
78 ldr r0, [pc, #-4092]
86 stmfd sp!, {r0-r3}
91 ldr r0, [pc, #-4092]
[all …]
/external/llvm/test/MC/ARM/
Darm-shift-encoding.s3 ldr r0, [r0, r0]
4 ldr r0, [r0, r0, lsr #32]
5 ldr r0, [r0, r0, lsr #16]
6 ldr r0, [r0, r0, lsl #0]
7 ldr r0, [r0, r0, lsl #16]
8 ldr r0, [r0, r0, asr #32]
9 ldr r0, [r0, r0, asr #16]
10 ldr r0, [r0, r0, rrx]
11 ldr r0, [r0, r0, ror #16]
13 @ CHECK: ldr r0, [r0, r0] @ encoding: [0x00,0x00,0x90,0xe7]
[all …]
Dneont2-vld-encoding.s5 @ CHECK: vld1.8 {d16}, [r0:64] @ encoding: [0x60,0xf9,0x1f,0x07]
6 vld1.8 {d16}, [r0:64]
7 @ CHECK: vld1.16 {d16}, [r0] @ encoding: [0x60,0xf9,0x4f,0x07]
8 vld1.16 {d16}, [r0]
9 @ CHECK: vld1.32 {d16}, [r0] @ encoding: [0x60,0xf9,0x8f,0x07]
10 vld1.32 {d16}, [r0]
11 @ CHECK: vld1.64 {d16}, [r0] @ encoding: [0x60,0xf9,0xcf,0x07]
12 vld1.64 {d16}, [r0]
13 @ CHECK: vld1.8 {d16, d17}, [r0:64] @ encoding: [0x60,0xf9,0x1f,0x0a]
14 vld1.8 {d16, d17}, [r0:64]
[all …]
Dthumb_rewrites.s10 adds r0, r0, #8
11 @ CHECK: adds r0, #8 @ encoding: [0x08,0x30]
13 adds r0, r0, r0
14 @ CHECK: adds r0, r0, r0 @ encoding: [0x00,0x18]
16 add r0, r0, r8
17 @ CHECK: add r0, r8 @ encoding: [0x40,0x44]
22 add sp, sp, r0
23 @ CHECK: add sp, r0 @ encoding: [0x85,0x44]
38 add r0, r0, r1
39 @ CHECK: add r0, r1 @ encoding: [0x08,0x44]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Darm-shift-encoding.s3 ldr r0, [r0, r0]
4 ldr r0, [r0, r0, lsr #32]
5 ldr r0, [r0, r0, lsr #16]
6 ldr r0, [r0, r0, lsl #0]
7 ldr r0, [r0, r0, lsl #16]
8 ldr r0, [r0, r0, asr #32]
9 ldr r0, [r0, r0, asr #16]
10 ldr r0, [r0, r0, rrx]
11 ldr r0, [r0, r0, ror #16]
13 @ CHECK: ldr r0, [r0, r0] @ encoding: [0x00,0x00,0x90,0xe7]
[all …]
Dneont2-vld-encoding.s5 @ CHECK: vld1.8 {d16}, [r0:64] @ encoding: [0x60,0xf9,0x1f,0x07]
6 vld1.8 {d16}, [r0:64]
7 @ CHECK: vld1.16 {d16}, [r0] @ encoding: [0x60,0xf9,0x4f,0x07]
8 vld1.16 {d16}, [r0]
9 @ CHECK: vld1.32 {d16}, [r0] @ encoding: [0x60,0xf9,0x8f,0x07]
10 vld1.32 {d16}, [r0]
11 @ CHECK: vld1.64 {d16}, [r0] @ encoding: [0x60,0xf9,0xcf,0x07]
12 vld1.64 {d16}, [r0]
13 @ CHECK: vld1.8 {d16, d17}, [r0:64] @ encoding: [0x60,0xf9,0x1f,0x0a]
14 vld1.8 {d16, d17}, [r0:64]
[all …]
Dthumb_rewrites.s10 adds r0, r0, #8
11 @ CHECK: adds r0, #8 @ encoding: [0x08,0x30]
13 adds r0, r0, r0
14 @ CHECK: adds r0, r0, r0 @ encoding: [0x00,0x18]
16 add r0, r0, r8
17 @ CHECK: add r0, r8 @ encoding: [0x40,0x44]
22 add sp, sp, r0
23 @ CHECK: add sp, r0 @ encoding: [0x85,0x44]
38 add r0, r0, r1
39 @ CHECK: add r0, r1 @ encoding: [0x08,0x44]
[all …]
/external/vixl/test/aarch32/
Dtest-assembler-cond-rd-sp-operand-imm8-t32.cc95 {{{al, r0, sp, 0x0}, false, al, "al r0 sp 0x0", "al_r0_sp_0x0"},
96 {{al, r0, sp, 0x4}, false, al, "al r0 sp 0x4", "al_r0_sp_0x4"},
97 {{al, r0, sp, 0x8}, false, al, "al r0 sp 0x8", "al_r0_sp_0x8"},
98 {{al, r0, sp, 0xc}, false, al, "al r0 sp 0xc", "al_r0_sp_0xc"},
99 {{al, r0, sp, 0x10}, false, al, "al r0 sp 0x10", "al_r0_sp_0x10"},
100 {{al, r0, sp, 0x14}, false, al, "al r0 sp 0x14", "al_r0_sp_0x14"},
101 {{al, r0, sp, 0x18}, false, al, "al r0 sp 0x18", "al_r0_sp_0x18"},
102 {{al, r0, sp, 0x1c}, false, al, "al r0 sp 0x1c", "al_r0_sp_0x1c"},
103 {{al, r0, sp, 0x20}, false, al, "al r0 sp 0x20", "al_r0_sp_0x20"},
104 {{al, r0, sp, 0x24}, false, al, "al r0 sp 0x24", "al_r0_sp_0x24"},
[all …]
Dtest-simulator-cond-rdlow-operand-imm8-t32.cc190 const TestLoopData kTests[] = {{{eq, r0, 0},
195 {{ne, r0, 0},
200 {{cs, r0, 0},
205 {{cc, r0, 0},
210 {{mi, r0, 0},
215 {{pl, r0, 0},
220 {{vs, r0, 0},
225 {{vc, r0, 0},
230 {{hi, r0, 0},
235 {{ls, r0, 0},
[all …]
/external/u-boot/arch/arm/mach-orion5x/
Dlowlevel_init.S87 ldr r0, =0x00000001
88 str r0, [r3, #0x480]
94 ldr r0, =0x00000030
95 str r0, [r3, #0xd00]
101 mov r0, #0
102 str r0, [r3, #0x504]
103 str r0, [r3, #0x50C]
104 str r0, [r3, #0x514]
105 str r0, [r3, #0x51C]
108 ldr r0, =SDRAM_CONFIG
[all …]
/external/capstone/suite/MC/ARM/
Darm-shift-encoding.s.cs2 0x00,0x00,0x90,0xe7 = ldr r0, [r0, r0]
3 0x20,0x00,0x90,0xe7 = ldr r0, [r0, r0, lsr #32]
4 0x20,0x08,0x90,0xe7 = ldr r0, [r0, r0, lsr #16]
5 0x00,0x00,0x90,0xe7 = ldr r0, [r0, r0]
6 0x00,0x08,0x90,0xe7 = ldr r0, [r0, r0, lsl #16]
7 0x40,0x00,0x90,0xe7 = ldr r0, [r0, r0, asr #32]
8 0x40,0x08,0x90,0xe7 = ldr r0, [r0, r0, asr #16]
9 0x60,0x00,0x90,0xe7 = ldr r0, [r0, r0, rrx]
10 0x60,0x08,0x90,0xe7 = ldr r0, [r0, r0, ror #16]
11 0x00,0xf0,0xd0,0xf7 = pld [r0, r0]
[all …]
/external/swiftshader/third_party/subzero/tests_lit/assembler/arm32/
Ddiv-vec.ll61 ; ASM: udiv r0, r0, r1
62 ; ASM: udiv r0, r0, r1
63 ; ASM: udiv r0, r0, r1
64 ; ASM: udiv r0, r0, r1
84 ; ASM: uxth r0, r0
86 ; ASM: udiv r0, r0, r1
87 ; ASM: uxth r0, r0
89 ; ASM: udiv r0, r0, r1
90 ; ASM: uxth r0, r0
92 ; ASM: udiv r0, r0, r1
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dand-load-combine.ll11 ; ARM-NEXT: ldrb r0, [r0]
13 ; ARM-NEXT: eor r0, r1, r0
14 ; ARM-NEXT: clz r0, r0
15 ; ARM-NEXT: lsr r0, r0, #5
20 ; ARMEB-NEXT: ldrb r0, [r0, #1]
22 ; ARMEB-NEXT: eor r0, r1, r0
23 ; ARMEB-NEXT: clz r0, r0
24 ; ARMEB-NEXT: lsr r0, r0, #5
29 ; THUMB1-NEXT: ldrb r0, [r0]
31 ; THUMB1-NEXT: eors r1, r0
[all …]
/external/u-boot/board/samsung/goni/
Dlowlevel_init.S34 ldr r0, [r2]
36 and r0, r0, r1
37 cmp r0, r5
45 ldr r0, =S5PC110_RST_STAT
46 ldr r1, [r0]
53 addeq r0, r8, #0x280 @ S5PC100_GPIO_J4
54 addne r0, r8, #0x2C0 @ S5PC110_GPIO_J4
55 ldr r1, [r0, #0x0] @ GPIO_CON_OFFSET
58 str r1, [r0, #0x0] @ GPIO_CON_OFFSET
60 ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET
[all …]
/external/u-boot/board/freescale/mx6sllevk/
Dplugin.S10 ldr r0, =IOMUXC_BASE_ADDR
12 str r1, [r0, #0x550]
14 str r1, [r0, #0x534]
16 str r1, [r0, #0x2AC]
17 str r1, [r0, #0x548]
18 str r1, [r0, #0x52C]
20 str r1, [r0, #0x530]
22 str r1, [r0, #0x2B0]
23 str r1, [r0, #0x2B4]
24 str r1, [r0, #0x2B8]
[all …]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneon-vld-encoding.s4 vld1.8 {d16}, [r0, :64]
5 vld1.16 {d16}, [r0]
6 vld1.32 {d16}, [r0]
7 vld1.64 {d16}, [r0]
8 vld1.8 {d16, d17}, [r0, :64]
9 vld1.16 {d16, d17}, [r0, :128]
10 vld1.32 {d16, d17}, [r0]
11 vld1.64 {d16, d17}, [r0]
13 @ CHECK: vld1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x60,0xf4]
14 @ CHECK: vld1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x60,0xf4]
[all …]
Dneont2-vld-encoding.s6 @ CHECK: vld1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x60,0xf9]
7 vld1.8 {d16}, [r0, :64]
8 @ CHECK: vld1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x60,0xf9]
9 vld1.16 {d16}, [r0]
10 @ CHECK: vld1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x60,0xf9]
11 vld1.32 {d16}, [r0]
12 @ CHECK: vld1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x60,0xf9]
13 vld1.64 {d16}, [r0]
14 @ CHECK: vld1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x60,0xf9]
15 vld1.8 {d16, d17}, [r0, :64]
[all …]

12345678910>>...142