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Searched refs:r5 (Results 1 – 25 of 1466) sorted by relevance

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/external/linux-kselftest/tools/testing/selftests/powerpc/include/
Dvsx_asm.h18 li r5,0
19 lxvd2x vs20,r5,r3
20 addi r5,r5,16
21 lxvd2x vs21,r5,r3
22 addi r5,r5,16
23 lxvd2x vs22,r5,r3
24 addi r5,r5,16
25 lxvd2x vs23,r5,r3
26 addi r5,r5,16
27 lxvd2x vs24,r5,r3
[all …]
Dvmx_asm.h71 li r5,0
72 lvx v20,r5,r3
73 addi r5,r5,16
74 lvx v21,r5,r3
75 addi r5,r5,16
76 lvx v22,r5,r3
77 addi r5,r5,16
78 lvx v23,r5,r3
79 addi r5,r5,16
80 lvx v24,r5,r3
[all …]
/external/libxaac/decoder/armv7/
Dixheaacd_auto_corr.s35 MOV r5, #9728
36 LDR r4, [r12, r5]
37 ADD r5, r5, #256
38 LDR r3, [r12, r5]
41 LDR r5, [r12], #256
46 MOV r5, r5, ASR #3
49 SMULWT r9, r5, r6
71 SMLAWT r9, r5, r5, r9
72 SMLAWT r7, r4, r5, r7
77 SMLAWT r8, r6, r5, r8
[all …]
/external/capstone/suite/MC/ARM/
Dbasic-arm-instructions.s.cs14 0x06,0x40,0xa5,0xe0 = adc r4, r5, r6
15 0x86,0x40,0xa5,0xe0 = adc r4, r5, r6, lsl #1
16 0x86,0x4f,0xa5,0xe0 = adc r4, r5, r6, lsl #31
17 0xa6,0x40,0xa5,0xe0 = adc r4, r5, r6, lsr #1
18 0xa6,0x4f,0xa5,0xe0 = adc r4, r5, r6, lsr #31
19 0x26,0x40,0xa5,0xe0 = adc r4, r5, r6, lsr #32
20 0xc6,0x40,0xa5,0xe0 = adc r4, r5, r6, asr #1
21 0xc6,0x4f,0xa5,0xe0 = adc r4, r5, r6, asr #31
22 0x46,0x40,0xa5,0xe0 = adc r4, r5, r6, asr #32
23 0xe6,0x40,0xa5,0xe0 = adc r4, r5, r6, ror #1
[all …]
Dbasic-thumb2-instructions.s.cs8 0x43,0xf1,0x07,0x45 = adc r5, r3, #2264924160
11 0x45,0xeb,0x06,0x04 = adc.w r4, r5, r6
12 0x55,0xeb,0x06,0x04 = adcs.w r4, r5, r6
21 0x03,0xf2,0xff,0x35 = addwne r5, r3, #1023
22 0x05,0xf2,0x25,0x14 = addweq r4, r5, #293
42 0x09,0xeb,0x22,0x05 = add.w r5, r9, r2, asr #32
52 0x05,0xf4,0x7f,0x22 = and r2, r5, #1044480
56 0x04,0xf0,0xff,0x35 = and r5, r4, #4294967295
61 0x15,0xea,0x12,0x54 = ands.w r4, r5, r2, lsr #20
77 0x6f,0xf3,0xd3,0x05 = bfc r5, #3, #17
[all …]
/external/vixl/test/aarch32/
Dtest-assembler-cond-rdlow-rnlow-rmlow-in-it-block-t32.cc100 {{eq, r0, r5, r0}, true, eq, "eq r0 r5 r0", "eq_r0_r5_r0"},
108 {{eq, r1, r5, r1}, true, eq, "eq r1 r5 r1", "eq_r1_r5_r1"},
116 {{eq, r2, r5, r2}, true, eq, "eq r2 r5 r2", "eq_r2_r5_r2"},
124 {{eq, r3, r5, r3}, true, eq, "eq r3 r5 r3", "eq_r3_r5_r3"},
132 {{eq, r4, r5, r4}, true, eq, "eq r4 r5 r4", "eq_r4_r5_r4"},
135 {{eq, r5, r0, r5}, true, eq, "eq r5 r0 r5", "eq_r5_r0_r5"},
136 {{eq, r5, r1, r5}, true, eq, "eq r5 r1 r5", "eq_r5_r1_r5"},
137 {{eq, r5, r2, r5}, true, eq, "eq r5 r2 r5", "eq_r5_r2_r5"},
138 {{eq, r5, r3, r5}, true, eq, "eq r5 r3 r5", "eq_r5_r3_r5"},
139 {{eq, r5, r4, r5}, true, eq, "eq r5 r4 r5", "eq_r5_r4_r5"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-all-low-rd-is-rn-in-it-block-t32.cc109 {{eq, r5, r5, r2}, true, eq, "eq r5 r5 r2", "eq_r5_r5_r2"},
114 {{eq, r5, r5, r5}, true, eq, "eq r5 r5 r5", "eq_r5_r5_r5"},
118 {{mi, r5, r5, r3}, true, mi, "mi r5 r5 r3", "mi_r5_r5_r3"},
124 {{vs, r7, r7, r5}, true, vs, "vs r7 r7 r5", "vs_r7_r7_r5"},
126 {{le, r5, r5, r3}, true, le, "le r5 r5 r3", "le_r5_r5_r3"},
127 {{vs, r1, r1, r5}, true, vs, "vs r1 r1 r5", "vs_r1_r1_r5"},
130 {{cc, r2, r2, r5}, true, cc, "cc r2 r2 r5", "cc_r2_r2_r5"},
136 {{hi, r5, r5, r7}, true, hi, "hi r5 r5 r7", "hi_r5_r5_r7"},
139 {{ls, r5, r5, r4}, true, ls, "ls r5 r5 r4", "ls_r5_r5_r4"},
145 {{ls, r5, r5, r0}, true, ls, "ls r5 r5 r0", "ls_r5_r5_r0"},
[all …]
Dtest-assembler-cond-rd-rn-operand-rm-all-low-in-it-block-t32.cc97 {{{cs, r7, r1, r5}, true, cs, "cs r7 r1 r5", "cs_r7_r1_r5"},
100 {{pl, r5, r3, r4}, true, pl, "pl r5 r3 r4", "pl_r5_r3_r4"},
107 {{ne, r5, r1, r0}, true, ne, "ne r5 r1 r0", "ne_r5_r1_r0"},
114 {{le, r5, r5, r4}, true, le, "le r5 r5 r4", "le_r5_r5_r4"},
119 {{vs, r4, r5, r7}, true, vs, "vs r4 r5 r7", "vs_r4_r5_r7"},
121 {{lt, r3, r5, r2}, true, lt, "lt r3 r5 r2", "lt_r3_r5_r2"},
126 {{cs, r7, r2, r5}, true, cs, "cs r7 r2 r5", "cs_r7_r2_r5"},
128 {{cc, r5, r6, r6}, true, cc, "cc r5 r6 r6", "cc_r5_r6_r6"},
140 {{ge, r6, r5, r5}, true, ge, "ge r6 r5 r5", "ge_r6_r5_r5"},
141 {{le, r6, r5, r1}, true, le, "le r6 r5 r1", "le_r6_r5_r1"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-imm8-t32.cc1377 {{al, r5, r5, 0}, false, al, "al r5 r5 0", "al_r5_r5_0"},
1378 {{al, r5, r5, 1}, false, al, "al r5 r5 1", "al_r5_r5_1"},
1379 {{al, r5, r5, 2}, false, al, "al r5 r5 2", "al_r5_r5_2"},
1380 {{al, r5, r5, 3}, false, al, "al r5 r5 3", "al_r5_r5_3"},
1381 {{al, r5, r5, 4}, false, al, "al r5 r5 4", "al_r5_r5_4"},
1382 {{al, r5, r5, 5}, false, al, "al r5 r5 5", "al_r5_r5_5"},
1383 {{al, r5, r5, 6}, false, al, "al r5 r5 6", "al_r5_r5_6"},
1384 {{al, r5, r5, 7}, false, al, "al r5 r5 7", "al_r5_r5_7"},
1385 {{al, r5, r5, 8}, false, al, "al r5 r5 8", "al_r5_r5_8"},
1386 {{al, r5, r5, 9}, false, al, "al r5 r5 9", "al_r5_r5_9"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-imm8-in-it-block-t32.cc99 {{cc, r5, r5, 72}, true, cc, "cc r5 r5 72", "cc_r5_r5_72"},
102 {{vc, r5, r5, 114}, true, vc, "vc r5 r5 114", "vc_r5_r5_114"},
107 {{vs, r5, r5, 195}, true, vs, "vs r5 r5 195", "vs_r5_r5_195"},
110 {{mi, r5, r5, 220}, true, mi, "mi r5 r5 220", "mi_r5_r5_220"},
118 {{ls, r5, r5, 89}, true, ls, "ls r5 r5 89", "ls_r5_r5_89"},
119 {{ls, r5, r5, 32}, true, ls, "ls r5 r5 32", "ls_r5_r5_32"},
123 {{mi, r5, r5, 167}, true, mi, "mi r5 r5 167", "mi_r5_r5_167"},
126 {{ge, r5, r5, 242}, true, ge, "ge r5 r5 242", "ge_r5_r5_242"},
131 {{eq, r5, r5, 162}, true, eq, "eq r5 r5 162", "eq_r5_r5_162"},
132 {{gt, r5, r5, 139}, true, gt, "gt r5 r5 139", "gt_r5_r5_139"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-imm3-in-it-block-t32.cc100 {{cc, r5, r1, 6}, true, cc, "cc r5 r1 6", "cc_r5_r1_6"},
101 {{cs, r5, r2, 0}, true, cs, "cs r5 r2 0", "cs_r5_r2_0"},
102 {{vs, r5, r6, 7}, true, vs, "vs r5 r6 7", "vs_r5_r6_7"},
105 {{lt, r4, r5, 7}, true, lt, "lt r4 r5 7", "lt_r4_r5_7"},
109 {{vc, r5, r2, 5}, true, vc, "vc r5 r2 5", "vc_r5_r2_5"},
111 {{cs, r2, r5, 4}, true, cs, "cs r2 r5 4", "cs_r2_r5_4"},
112 {{ge, r7, r5, 7}, true, ge, "ge r7 r5 7", "ge_r7_r5_7"},
121 {{lt, r5, r2, 0}, true, lt, "lt r5 r2 0", "lt_r5_r2_0"},
123 {{ne, r5, r7, 4}, true, ne, "ne r5 r7 4", "ne_r5_r7_4"},
124 {{le, r5, r3, 2}, true, le, "le r5 r3 2", "le_r5_r3_2"},
[all …]
Dtest-assembler-cond-rd-operand-rn-low-registers-in-it-block-t32.cc100 {{eq, r0, r5}, true, eq, "eq r0 r5", "eq_r0_r5"},
108 {{eq, r1, r5}, true, eq, "eq r1 r5", "eq_r1_r5"},
116 {{eq, r2, r5}, true, eq, "eq r2 r5", "eq_r2_r5"},
124 {{eq, r3, r5}, true, eq, "eq r3 r5", "eq_r3_r5"},
132 {{eq, r4, r5}, true, eq, "eq r4 r5", "eq_r4_r5"},
135 {{eq, r5, r0}, true, eq, "eq r5 r0", "eq_r5_r0"},
136 {{eq, r5, r1}, true, eq, "eq r5 r1", "eq_r5_r1"},
137 {{eq, r5, r2}, true, eq, "eq r5 r2", "eq_r5_r2"},
138 {{eq, r5, r3}, true, eq, "eq r5 r3", "eq_r5_r3"},
139 {{eq, r5, r4}, true, eq, "eq r5 r4", "eq_r5_r4"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-zero-in-it-block-t32.cc100 {{eq, r0, r5, 0}, true, eq, "eq r0 r5 0", "eq_r0_r5_0"},
108 {{eq, r1, r5, 0}, true, eq, "eq r1 r5 0", "eq_r1_r5_0"},
116 {{eq, r2, r5, 0}, true, eq, "eq r2 r5 0", "eq_r2_r5_0"},
124 {{eq, r3, r5, 0}, true, eq, "eq r3 r5 0", "eq_r3_r5_0"},
132 {{eq, r4, r5, 0}, true, eq, "eq r4 r5 0", "eq_r4_r5_0"},
135 {{eq, r5, r0, 0}, true, eq, "eq r5 r0 0", "eq_r5_r0_0"},
136 {{eq, r5, r1, 0}, true, eq, "eq r5 r1 0", "eq_r5_r1_0"},
137 {{eq, r5, r2, 0}, true, eq, "eq r5 r2 0", "eq_r5_r2_0"},
138 {{eq, r5, r3, 0}, true, eq, "eq r5 r3 0", "eq_r5_r3_0"},
139 {{eq, r5, r4, 0}, true, eq, "eq r5 r4 0", "eq_r5_r4_0"},
[all …]
Dtest-assembler-cond-rd-operand-rn-shift-rs-in-it-block-t32.cc104 {{hi, r6, r6, ROR, r5}, true, hi, "hi r6 r6 ROR r5", "hi_r6_r6_ROR_r5"},
108 {{mi, r4, r4, LSL, r5}, true, mi, "mi r4 r4 LSL r5", "mi_r4_r4_LSL_r5"},
109 {{le, r5, r5, LSR, r6}, true, le, "le r5 r5 LSR r6", "le_r5_r5_LSR_r6"},
112 {{hi, r5, r5, LSL, r6}, true, hi, "hi r5 r5 LSL r6", "hi_r5_r5_LSL_r6"},
116 {{eq, r5, r5, ROR, r2}, true, eq, "eq r5 r5 ROR r2", "eq_r5_r5_ROR_r2"},
117 {{eq, r5, r5, LSR, r1}, true, eq, "eq r5 r5 LSR r1", "eq_r5_r5_LSR_r1"},
130 {{mi, r5, r5, LSL, r5}, true, mi, "mi r5 r5 LSL r5", "mi_r5_r5_LSL_r5"},
134 {{vc, r5, r5, ROR, r3}, true, vc, "vc r5 r5 ROR r3", "vc_r5_r5_ROR_r3"},
143 {{gt, r5, r5, ROR, r0}, true, gt, "gt r5 r5 ROR r0", "gt_r5_r5_ROR_r0"},
146 {{vs, r5, r5, ASR, r2}, true, vs, "vs r5 r5 ASR r2", "vs_r5_r5_ASR_r2"},
[all …]
Dtest-assembler-cond-rdlow-rnlow-operand-immediate-imm3-t32.cc137 {{al, r0, r5, 0}, false, al, "al r0 r5 0", "al_r0_r5_0"},
138 {{al, r0, r5, 1}, false, al, "al r0 r5 1", "al_r0_r5_1"},
139 {{al, r0, r5, 2}, false, al, "al r0 r5 2", "al_r0_r5_2"},
140 {{al, r0, r5, 3}, false, al, "al r0 r5 3", "al_r0_r5_3"},
141 {{al, r0, r5, 4}, false, al, "al r0 r5 4", "al_r0_r5_4"},
142 {{al, r0, r5, 5}, false, al, "al r0 r5 5", "al_r0_r5_5"},
143 {{al, r0, r5, 6}, false, al, "al r0 r5 6", "al_r0_r5_6"},
144 {{al, r0, r5, 7}, false, al, "al r0 r5 7", "al_r0_r5_7"},
201 {{al, r1, r5, 0}, false, al, "al r1 r5 0", "al_r1_r5_0"},
202 {{al, r1, r5, 1}, false, al, "al r1 r5 1", "al_r1_r5_1"},
[all …]
/external/u-boot/arch/powerpc/lib/
Dppcstring.S12 addi r5,r3,-1
16 stbu r0,1(r5)
22 cmpwi 0,r5,0
24 mtctr r5
35 addi r5,r3,-1
37 1: lbzu r0,1(r5)
40 addi r5,r5,-1
43 stbu r0,1(r5)
49 addi r5,r3,-1
51 1: lbzu r3,1(r5)
[all …]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dbasic-arm-instructions.s48 adc r4, r5, r6
50 adc r4, r5, r6, lsl #1
51 adc r4, r5, r6, lsl #31
52 adc r4, r5, r6, lsr #1
53 adc r4, r5, r6, lsr #31
54 adc r4, r5, r6, lsr #32
55 adc r4, r5, r6, asr #1
56 adc r4, r5, r6, asr #31
57 adc r4, r5, r6, asr #32
58 adc r4, r5, r6, ror #1
[all …]
Dbasic-thumb2-instructions.s26 adc r5, r3, #0x87000000
36 @ CHECK: adc r5, r3, #2264924160 @ encoding: [0x43,0xf1,0x07,0x45]
43 adc r4, r5, r6
44 adcs r4, r5, r6
52 @ CHECK: adc.w r4, r5, r6 @ encoding: [0x45,0xeb,0x06,0x04]
53 @ CHECK: adcs.w r4, r5, r6 @ encoding: [0x55,0xeb,0x06,0x04]
67 addwne r5, r3, #1023
68 addeq r4, r5, #293
79 @ CHECK: addwne r5, r3, #1023 @ encoding: [0x03,0xf2,0xff,0x35]
80 @ CHECK: addweq r4, r5, #293 @ encoding: [0x05,0xf2,0x25,0x14]
[all …]
/external/linux-kselftest/tools/testing/selftests/powerpc/math/
Dvmx_asm.S13 # Should be safe from C, only touches r4, r5 and v0,v1,v2
18 li r5,0
19 lvx v0,r5,r4
23 addi r5,r5,16
24 lvx v0,r5,r4
28 addi r5,r5,16
29 lvx v0,r5,r4
33 addi r5,r5,16
34 lvx v0,r5,r4
38 addi r5,r5,16
[all …]
/external/u-boot/arch/nios2/cpu/
Dstart.S34 movhi r5, %hi(ICACHE_SIZE_MAX)
35 ori r5, r5, %lo(ICACHE_SIZE_MAX)
36 0: initi r5
37 sub r5, r5, r4
38 bgt r5, r0, 0b
63 movhi r5, %hi(DCACHE_SIZE_MAX)
64 ori r5, r5, %lo(DCACHE_SIZE_MAX)
68 bltu r6, r5, 1b
77 _cur: movhi r5, %hi(_cur - _start)
78 ori r5, r5, %lo(_cur - _start)
[all …]
/external/u-boot/arch/sh/lib/
Dudivsi3_i4i-Os.S29 extu.w r5,r0
30 cmp/eq r5,r0
35 mov.l r5,@-r15
36 shll16 r5
38 div1 r5,r4
40 div1 r5,r4
41 div1 r5,r4
43 div1 r5,r4
48 div1 r5,r4
50 div1 r5,r4
[all …]
Dudivsi3_i4i.S45 cmp/hi r1,r5
46 extu.w r5,r1
48 cmp/eq r5,r1
51 mov r5,r1
52 shll16 r5
54 div1 r5,r0
56 div1 r5,r0
57 div1 r5,r0
59 div1 r5,r0
64 mov.b @(r0,r5),r1
[all …]
/external/skqp/src/compute/hs/cuda/sm_35/u64/
Dhs_cuda_u64.cu34 HS_KEY_TYPE r5 = HS_SLAB_GLOBAL_LOAD(vin, 4); variable
38 HS_CMP_XCHG(r1, r5);
44 HS_CMP_XCHG(r5, r7);
46 HS_CMP_XCHG(r3, r5);
50 HS_CMP_XCHG(r5, r6);
52 HS_CMP_XCHG(r2, r5);
55 HS_CMP_XCHG(r4, r5);
62 HS_CMP_FLIP(3, r4, r5);
64 HS_CMP_XCHG(r1, r5);
67 HS_CMP_XCHG(r5, r7);
[all …]
/external/skia/src/compute/hs/cuda/sm_35/u64/
Dhs_cuda_u64.cu34 HS_KEY_TYPE r5 = HS_SLAB_GLOBAL_LOAD(vin, 4); variable
38 HS_CMP_XCHG(r1, r5);
44 HS_CMP_XCHG(r5, r7);
46 HS_CMP_XCHG(r3, r5);
50 HS_CMP_XCHG(r5, r6);
52 HS_CMP_XCHG(r2, r5);
55 HS_CMP_XCHG(r4, r5);
62 HS_CMP_FLIP(3, r4, r5);
64 HS_CMP_XCHG(r1, r5);
67 HS_CMP_XCHG(r5, r7);
[all …]
/external/compiler-rt/lib/tsan/rtl/
Dtsan_rtl_ppc64.S55 addi r5,r1,48 // original stack ptr of caller
56 xor r5,r6,r5
57 std r5,0(r3) // mangled stack ptr of caller
58 ld r5,24(r1)
59 std r5,8(r3) // caller's saved TOC pointer
101 addi r5,r3,320
104 addi r6,r5,16
105 stvx v20,0,r5
106 addi r5,r5,32
109 stvx v22,0,r5
[all …]

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