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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dwrong-transalu-pos-fix.ll1 ; RUN: llc -march=r600 -mcpu=redwood -mtriple=r600-- < %s | FileCheck %s
9 %x.i = tail call i32 @llvm.r600.read.global.size.x() #1
10 %y.i18 = tail call i32 @llvm.r600.read.global.size.y() #1
12 %z.i17 = tail call i32 @llvm.r600.read.global.size.z() #1
14 %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #1
15 %x.i12.i = tail call i32 @llvm.r600.read.local.size.x() #1
17 %x.i4.i = tail call i32 @llvm.r600.read.tidig.x() #1
20 %y.i.i = tail call i32 @llvm.r600.read.tgid.y() #1
21 %y.i14.i = tail call i32 @llvm.r600.read.local.size.y() #1
23 %y.i6.i = tail call i32 @llvm.r600.read.tidig.y() #1
[all …]
Dannotate-kernel-features.ll3 declare i32 @llvm.r600.read.tgid.x() #0
4 declare i32 @llvm.r600.read.tgid.y() #0
5 declare i32 @llvm.r600.read.tgid.z() #0
7 declare i32 @llvm.r600.read.tidig.x() #0
8 declare i32 @llvm.r600.read.tidig.y() #0
9 declare i32 @llvm.r600.read.tidig.z() #0
11 declare i32 @llvm.r600.read.local.size.x() #0
12 declare i32 @llvm.r600.read.local.size.y() #0
13 declare i32 @llvm.r600.read.local.size.z() #0
17 %val = call i32 @llvm.r600.read.tgid.x()
[all …]
Damdgpu.work-item-intrinsics.deprecated.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
17 %0 = call i32 @llvm.r600.read.ngroups.x() #0
32 %0 = call i32 @llvm.r600.read.ngroups.y() #0
47 %0 = call i32 @llvm.r600.read.ngroups.z() #0
62 %0 = call i32 @llvm.r600.read.global.size.x() #0
77 %0 = call i32 @llvm.r600.read.global.size.y() #0
92 %0 = call i32 @llvm.r600.read.global.size.z() #0
107 %0 = call i32 @llvm.r600.read.local.size.x() #0
122 %0 = call i32 @llvm.r600.read.local.size.y() #0
137 %0 = call i32 @llvm.r600.read.local.size.z() #0
[all …]
Dfetch-limits.r700+.ll1 ; RUN: llc < %s -march=r600 -mcpu=rv710 | FileCheck %s
2 ; RUN: llc < %s -march=r600 -mcpu=rv730 | FileCheck %s
3 ; RUN: llc < %s -march=r600 -mcpu=rv770 | FileCheck %s
4 ; RUN: llc < %s -march=r600 -mcpu=cedar | FileCheck %s
5 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
6 ; RUN: llc < %s -march=r600 -mcpu=sumo | FileCheck %s
7 ; RUN: llc < %s -march=r600 -mcpu=juniper | FileCheck %s
8 ; RUN: llc < %s -march=r600 -mcpu=cypress | FileCheck %s
9 ; RUN: llc < %s -march=r600 -mcpu=barts | FileCheck %s
10 ; RUN: llc < %s -march=r600 -mcpu=turks | FileCheck %s
[all …]
Dr600.work-item-intrinsics.ll1 ; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | \
8 %0 = call i32 @llvm.r600.read.tgid.x() #0
18 %0 = call i32 @llvm.r600.read.tgid.y() #0
28 %0 = call i32 @llvm.r600.read.tgid.z() #0
37 %0 = call i32 @llvm.r600.read.tidig.x() #0
47 %0 = call i32 @llvm.r600.read.tidig.y() #0
57 %0 = call i32 @llvm.r600.read.tidig.z() #0
69 %implicitarg.ptr = call noalias i8 addrspace(7)* @llvm.r600.implicitarg.ptr()
81 %implicitarg.ptr = call noalias i8 addrspace(7)* @llvm.r600.implicitarg.ptr()
89 declare i8 addrspace(7)* @llvm.r600.implicitarg.ptr() #0
[all …]
Dfetch-limits.r600.ll1 ; RUN: llc < %s -march=r600 -mcpu=r600 | FileCheck %s
2 ; RUN: llc < %s -march=r600 -mcpu=rs880 | FileCheck %s
3 ; RUN: llc < %s -march=r600 -mcpu=rv670 | FileCheck %s
22 …%tmp10 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp9, i32 0, i32 0, i32 0, i32 0, i32 0, i32…
24 …%tmp12 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp11, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
26 …%tmp14 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp13, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
28 …%tmp16 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp15, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
30 …%tmp18 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp17, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
32 …%tmp20 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp19, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
34 …%tmp22 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp21, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
[all …]
Dllvm.r600.tex.ll1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
24 …%tmp1 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1…
26 …%tmp3 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp2, i32 0, i32 0, i32 0, i32 0, i32 0, i32 …
28 …%tmp5 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp4, i32 0, i32 0, i32 0, i32 0, i32 0, i32 …
30 …%tmp7 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp6, i32 0, i32 0, i32 0, i32 0, i32 0, i32 …
32 …%tmp9 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 …
34 …%tmp11 = call <4 x float> @llvm.r600.texc(<4 x float> %tmp10, i32 0, i32 0, i32 0, i32 0, i32 0, i…
36 …%tmp13 = call <4 x float> @llvm.r600.texc(<4 x float> %tmp12, i32 0, i32 0, i32 0, i32 0, i32 0, i…
38 …%tmp15 = call <4 x float> @llvm.r600.texc(<4 x float> %tmp14, i32 0, i32 0, i32 0, i32 0, i32 0, i…
40 …%tmp17 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp16, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
[all …]
Drv7x0_count3.ll1 ; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rv710 | FileCheck %s
15 …%tmp9 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 …
17 …%tmp11 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp10, i32 0, i32 0, i32 0, i32 1, i32 0, i3…
19 …%tmp13 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp12, i32 0, i32 0, i32 0, i32 2, i32 0, i3…
21 …%tmp15 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp14, i32 0, i32 0, i32 0, i32 3, i32 0, i3…
23 …%tmp17 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp16, i32 0, i32 0, i32 0, i32 4, i32 0, i3…
25 …%tmp19 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp18, i32 0, i32 0, i32 0, i32 5, i32 0, i3…
27 …%tmp21 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp20, i32 0, i32 0, i32 0, i32 6, i32 0, i3…
29 …%tmp23 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp22, i32 0, i32 0, i32 0, i32 7, i32 0, i3…
31 …%tmp25 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp24, i32 0, i32 0, i32 0, i32 8, i32 0, i3…
[all …]
Dllvm.r600.group.barrier.ll1 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG %s
7 %tmp = call i32 @llvm.r600.read.tidig.x()
10 call void @llvm.r600.group.barrier()
11 %tmp2 = call i32 @llvm.r600.read.local.size.x()
21 declare void @llvm.r600.group.barrier() #1
24 declare i32 @llvm.r600.read.tidig.x() #2
27 declare i32 @llvm.r600.read.local.size.x() #2
Dllvm.r600.read.local.size.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
19 %0 = call i32 @llvm.r600.read.local.size.x() #0
34 %0 = call i32 @llvm.r600.read.local.size.y() #0
49 %0 = call i32 @llvm.r600.read.local.size.z() #0
64 %x = call i32 @llvm.r600.read.local.size.x() #0
65 %y = call i32 @llvm.r600.read.local.size.y() #0
83 %x = call i32 @llvm.r600.read.local.size.x() #0
84 %z = call i32 @llvm.r600.read.local.size.z() #0
103 %y = call i32 @llvm.r600.read.local.size.y() #0
104 %z = call i32 @llvm.r600.read.local.size.z() #0
[all …]
Dtexture-input-merge.ll1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
19 …%14 = call <4 x float> @llvm.r600.tex(<4 x float> %10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i…
20 …%15 = call <4 x float> @llvm.r600.tex(<4 x float> %12, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i…
21 …%16 = call <4 x float> @llvm.r600.tex(<4 x float> %13, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i…
24 call void @llvm.r600.store.swizzle(<4 x float> %18, i32 0, i32 0)
28 declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readno…
29 declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
Dtex-clause-antidep.ll1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
15 …%9 = call <4 x float> @llvm.r600.tex(<4 x float> %8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32…
16 …%10 = call <4 x float> @llvm.r600.tex(<4 x float> %8, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
18 call void @llvm.r600.store.swizzle(<4 x float> %11, i32 0, i32 0)
22 declare <4 x float> @llvm.r600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readno…
23 declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)
/external/llvm/test/CodeGen/AMDGPU/
Dwrong-transalu-pos-fix.ll1 ; RUN: llc -march=r600 -mcpu=redwood -mtriple=r600-- < %s | FileCheck %s
9 %x.i = tail call i32 @llvm.r600.read.global.size.x() #1
10 %y.i18 = tail call i32 @llvm.r600.read.global.size.y() #1
12 %z.i17 = tail call i32 @llvm.r600.read.global.size.z() #1
14 %x.i.i = tail call i32 @llvm.r600.read.tgid.x() #1
15 %x.i12.i = tail call i32 @llvm.r600.read.local.size.x() #1
17 %x.i4.i = tail call i32 @llvm.r600.read.tidig.x() #1
20 %y.i.i = tail call i32 @llvm.r600.read.tgid.y() #1
21 %y.i14.i = tail call i32 @llvm.r600.read.local.size.y() #1
23 %y.i6.i = tail call i32 @llvm.r600.read.tidig.y() #1
[all …]
Dannotate-kernel-features.ll3 declare i32 @llvm.r600.read.tgid.x() #0
4 declare i32 @llvm.r600.read.tgid.y() #0
5 declare i32 @llvm.r600.read.tgid.z() #0
7 declare i32 @llvm.r600.read.tidig.x() #0
8 declare i32 @llvm.r600.read.tidig.y() #0
9 declare i32 @llvm.r600.read.tidig.z() #0
11 declare i32 @llvm.r600.read.local.size.x() #0
12 declare i32 @llvm.r600.read.local.size.y() #0
13 declare i32 @llvm.r600.read.local.size.z() #0
17 %val = call i32 @llvm.r600.read.tgid.x()
[all …]
Dr600.work-item-intrinsics.ll1 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
7 %0 = call i32 @llvm.r600.read.tgid.x() #0
16 %0 = call i32 @llvm.r600.read.tgid.y() #0
25 %0 = call i32 @llvm.r600.read.tgid.z() #0
34 %0 = call i32 @llvm.r600.read.tidig.x() #0
43 %0 = call i32 @llvm.r600.read.tidig.y() #0
52 %0 = call i32 @llvm.r600.read.tidig.z() #0
61 %implicitarg.ptr = call noalias i8 addrspace(7)* @llvm.r600.implicitarg.ptr()
73 %implicitarg.ptr = call noalias i8 addrspace(7)* @llvm.r600.implicitarg.ptr()
90 %0 = call i32 @llvm.r600.read.workdim() #0
[all …]
Damdgpu.work-item-intrinsics.deprecated.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
32 %0 = call i32 @llvm.r600.read.ngroups.x() #0
47 %0 = call i32 @llvm.r600.read.ngroups.y() #0
62 %0 = call i32 @llvm.r600.read.ngroups.z() #0
77 %0 = call i32 @llvm.r600.read.global.size.x() #0
92 %0 = call i32 @llvm.r600.read.global.size.y() #0
107 %0 = call i32 @llvm.r600.read.global.size.z() #0
122 %0 = call i32 @llvm.r600.read.local.size.x() #0
137 %0 = call i32 @llvm.r600.read.local.size.y() #0
152 %0 = call i32 @llvm.r600.read.local.size.z() #0
[all …]
Dfetch-limits.r700+.ll1 ; RUN: llc < %s -march=r600 -mcpu=rv710 | FileCheck %s
2 ; RUN: llc < %s -march=r600 -mcpu=rv730 | FileCheck %s
3 ; RUN: llc < %s -march=r600 -mcpu=rv770 | FileCheck %s
4 ; RUN: llc < %s -march=r600 -mcpu=cedar | FileCheck %s
5 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
6 ; RUN: llc < %s -march=r600 -mcpu=sumo | FileCheck %s
7 ; RUN: llc < %s -march=r600 -mcpu=juniper | FileCheck %s
8 ; RUN: llc < %s -march=r600 -mcpu=cypress | FileCheck %s
9 ; RUN: llc < %s -march=r600 -mcpu=barts | FileCheck %s
10 ; RUN: llc < %s -march=r600 -mcpu=turks | FileCheck %s
[all …]
Dllvm.r600.tex.ll1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
24 …%tmp1 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1…
26 …%tmp3 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp2, i32 0, i32 0, i32 0, i32 0, i32 0, i32 …
28 …%tmp5 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp4, i32 0, i32 0, i32 0, i32 0, i32 0, i32 …
30 …%tmp7 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp6, i32 0, i32 0, i32 0, i32 0, i32 0, i32 …
32 …%tmp9 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 …
34 …%tmp11 = call <4 x float> @llvm.r600.texc(<4 x float> %tmp10, i32 0, i32 0, i32 0, i32 0, i32 0, i…
36 …%tmp13 = call <4 x float> @llvm.r600.texc(<4 x float> %tmp12, i32 0, i32 0, i32 0, i32 0, i32 0, i…
38 …%tmp15 = call <4 x float> @llvm.r600.texc(<4 x float> %tmp14, i32 0, i32 0, i32 0, i32 0, i32 0, i…
40 …%tmp17 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp16, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
[all …]
Dfetch-limits.r600.ll1 ; RUN: llc < %s -march=r600 -mcpu=r600 | FileCheck %s
2 ; RUN: llc < %s -march=r600 -mcpu=rs880 | FileCheck %s
3 ; RUN: llc < %s -march=r600 -mcpu=rv670 | FileCheck %s
22 …%tmp10 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp9, i32 0, i32 0, i32 0, i32 0, i32 0, i32…
24 …%tmp12 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp11, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
26 …%tmp14 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp13, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
28 …%tmp16 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp15, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
30 …%tmp18 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp17, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
32 …%tmp20 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp19, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
34 …%tmp22 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp21, i32 0, i32 0, i32 0, i32 0, i32 0, i3…
[all …]
Dllvm.r600.read.local.size.ll3 ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
19 %0 = call i32 @llvm.r600.read.local.size.x() #0
34 %0 = call i32 @llvm.r600.read.local.size.y() #0
49 %0 = call i32 @llvm.r600.read.local.size.z() #0
64 %x = call i32 @llvm.r600.read.local.size.x() #0
65 %y = call i32 @llvm.r600.read.local.size.y() #0
83 %x = call i32 @llvm.r600.read.local.size.x() #0
84 %z = call i32 @llvm.r600.read.local.size.z() #0
103 %y = call i32 @llvm.r600.read.local.size.y() #0
104 %z = call i32 @llvm.r600.read.local.size.z() #0
[all …]
Drv7x0_count3.ll1 ; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rv710 | FileCheck %s
15 …%tmp9 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 …
17 …%tmp11 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp10, i32 0, i32 0, i32 0, i32 1, i32 0, i3…
19 …%tmp13 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp12, i32 0, i32 0, i32 0, i32 2, i32 0, i3…
21 …%tmp15 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp14, i32 0, i32 0, i32 0, i32 3, i32 0, i3…
23 …%tmp17 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp16, i32 0, i32 0, i32 0, i32 4, i32 0, i3…
25 …%tmp19 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp18, i32 0, i32 0, i32 0, i32 5, i32 0, i3…
27 …%tmp21 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp20, i32 0, i32 0, i32 0, i32 6, i32 0, i3…
29 …%tmp23 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp22, i32 0, i32 0, i32 0, i32 7, i32 0, i3…
31 …%tmp25 = call <4 x float> @llvm.r600.tex(<4 x float> %tmp24, i32 0, i32 0, i32 0, i32 8, i32 0, i3…
[all …]
/external/clang/test/Driver/
Dr600-mcpu.cl3 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=r600 %s -o - 2>&1 | FileCheck --check-pr…
4 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv630 %s -o - 2>&1 | FileCheck --check-p…
5 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv635 %s -o - 2>&1 | FileCheck --check-p…
6 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv610 %s -o - 2>&1 | FileCheck --check-p…
7 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv620 %s -o - 2>&1 | FileCheck --check-p…
8 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rs780 %s -o - 2>&1 | FileCheck --check-p…
9 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rs880 %s -o - 2>&1 | FileCheck --check-p…
10 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv670 %s -o - 2>&1 | FileCheck --check-p…
11 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv710 %s -o - 2>&1 | FileCheck --check-p…
12 // RUN: %clang -### -target r600 -x cl -S -emit-llvm -mcpu=rv730 %s -o - 2>&1 | FileCheck --check-p…
[all …]
/external/clang/test/CodeGenOpenCL/
Dbuiltins-r600.cl2 // RUN: %clang_cc1 -triple r600-unknown-unknown -target-cpu cypress -S -emit-llvm -o - %s | FileChe…
5 // CHECK: call float @llvm.r600.rsq.f32
13 // XCHECK: call double @llvm.r600.rsq.f64
37 // CHECK: call i8 addrspace(7)* @llvm.r600.implicitarg.ptr()
44 // CHECK: tail call i32 @llvm.r600.read.tgid.x()
45 // CHECK: tail call i32 @llvm.r600.read.tgid.y()
46 // CHECK: tail call i32 @llvm.r600.read.tgid.z()
58 // CHECK: tail call i32 @llvm.r600.read.tidig.x(), !range [[WI_RANGE:![0-9]*]]
59 // CHECK: tail call i32 @llvm.r600.read.tidig.y(), !range [[WI_RANGE]]
60 // CHECK: tail call i32 @llvm.r600.read.tidig.z(), !range [[WI_RANGE]]
/external/clang/test/Misc/
Dr600.languageOptsOpenCL.cl2 // RUN: %clang_cc1 -x cl -cl-std=CL %s -verify -triple r600-unknown-unknown -target-cpu cayman
3 // RUN: %clang_cc1 -x cl -cl-std=CL1.1 %s -verify -triple r600-unknown-unknown -target-cpu cayman
4 // RUN: %clang_cc1 -x cl -cl-std=CL1.2 %s -verify -triple r600-unknown-unknown -target-cpu cayman
5 // RUN: %clang_cc1 -x cl -cl-std=CL2.0 %s -verify -triple r600-unknown-unknown -target-cpu cayman
6 // RUN: %clang_cc1 -x cl -cl-std=CL %s -verify -triple r600-unknown-unknown -Wpedantic-core-feature…
7 // RUN: %clang_cc1 -x cl -cl-std=CL1.1 %s -verify -triple r600-unknown-unknown -Wpedantic-core-feat…
8 // RUN: %clang_cc1 -x cl -cl-std=CL1.2 %s -verify -triple r600-unknown-unknown -Wpedantic-core-feat…
9 // RUN: %clang_cc1 -x cl -cl-std=CL2.0 %s -verify -triple r600-unknown-unknown -Wpedantic-core-feat…
10 // RUN: %clang_cc1 -x cl -cl-std=CL %s -verify -triple r600-unknown-unknown -target-cpu cypress
11 // RUN: %clang_cc1 -x cl -cl-std=CL1.1 %s -verify -triple r600-unknown-unknown -target-cpu cypress
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/external/mesa3d/docs/
Dfeatures.txt36 GL 3.0, GLSL 1.30 --- all DONE: freedreno, i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr
68 GL 3.1, GLSL 1.40 --- all DONE: freedreno, i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr
81 GL 3.2, GLSL 1.50 --- all DONE: i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe, swr
96 GL 3.3, GLSL 3.30 --- all DONE: i965, nv50, nvc0, r600, radeonsi, llvmpipe, softpipe
110 GL 4.0, GLSL 4.00 --- all DONE: i965/gen7+, nvc0, r600, radeonsi
139 GL 4.1, GLSL 4.10 --- all DONE: i965/gen7+, nvc0, r600, radeonsi
149 GL 4.2, GLSL 4.20 -- all DONE: i965/gen7+, nvc0, r600, radeonsi
165 GL 4.3, GLSL 4.30 -- all DONE: i965/gen8+, nvc0, r600, radeonsi
194 …GL_ARB_buffer_storage DONE (freedreno, i965, nv50, r600, llvmpipe,…
195 …GL_ARB_clear_texture DONE (i965, nv50, r600, llvmpipe, softpipe, …
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