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Searched refs:radeon_set_context_reg (Results 1 – 18 of 18) sorted by relevance

/external/mesa3d/src/gallium/drivers/r600/
Dcayman_msaa.c149 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0); in cayman_emit_msaa_sample_locs()
150 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0); in cayman_emit_msaa_sample_locs()
151 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0); in cayman_emit_msaa_sample_locs()
152 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0); in cayman_emit_msaa_sample_locs()
155 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_2x[0]); in cayman_emit_msaa_sample_locs()
156 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_2x[1]); in cayman_emit_msaa_sample_locs()
157 radeon_set_context_reg(cs, CM_R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, eg_sample_locs_2x[2]); in cayman_emit_msaa_sample_locs()
158 radeon_set_context_reg(cs, CM_R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, eg_sample_locs_2x[3]); in cayman_emit_msaa_sample_locs()
161 radeon_set_context_reg(cs, CM_R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, eg_sample_locs_4x[0]); in cayman_emit_msaa_sample_locs()
162 radeon_set_context_reg(cs, CM_R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, eg_sample_locs_4x[1]); in cayman_emit_msaa_sample_locs()
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Dr600_state.c280 radeon_set_context_reg(cs, R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL, in r600_emit_polygon_offset()
1376 radeon_set_context_reg(cs, R_028040_CB_COLOR0_BASE + i*4, cb[i]->cb_color_base); in r600_emit_framebuffer_state()
1389 radeon_set_context_reg(cs, R_0280E0_CB_COLOR0_FRAG + i*4, cb[i]->cb_color_fmask); in r600_emit_framebuffer_state()
1402 radeon_set_context_reg(cs, R_0280C0_CB_COLOR0_TILE + i*4, cb[i]->cb_color_cmask); in r600_emit_framebuffer_state()
1461 radeon_set_context_reg(cs, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit); in r600_emit_framebuffer_state()
1467 radeon_set_context_reg(cs, R_028010_DB_DEPTH_INFO, S_028010_FORMAT(V_028010_DEPTH_INVALID)); in r600_emit_framebuffer_state()
1485 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, 1); in r600_emit_framebuffer_state()
1490 radeon_set_context_reg(cs, R_0287A0_CB_SHADER_CONTROL, in r600_emit_framebuffer_state()
1526 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control); in r600_emit_cb_misc_state()
1536 radeon_set_context_reg(cs, R_028808_CB_COLOR_CONTROL, in r600_emit_cb_misc_state()
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Dr600_streamout.c284 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0); in r600_emit_streamout_end()
318 radeon_set_context_reg(rctx->gfx.cs, strmout_buffer_reg, strmout_buffer_val); in r600_emit_streamout_enable()
319 radeon_set_context_reg(rctx->gfx.cs, strmout_config_reg, strmout_config_val); in r600_emit_streamout_enable()
Devergreen_state.c981 radeon_set_context_reg(cs, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, in evergreen_emit_config_state()
1675 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, in evergreen_emit_msaa_state()
1683 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1, in evergreen_emit_msaa_state()
1761 …radeon_set_context_reg(cs, R_028B9C_CB_IMMED0_BASE + (idx * 4), resource->immed_buffer->gpu_addres… in evergreen_emit_image_state()
1839 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, in evergreen_emit_framebuffer_state()
1890 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, in evergreen_emit_framebuffer_state()
1897 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0); in evergreen_emit_framebuffer_state()
1899 radeon_set_context_reg(cs, R_028E50_CB_COLOR8_INFO + (i - 8) * 0x1C, 0); in evergreen_emit_framebuffer_state()
1912 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view); in evergreen_emit_framebuffer_state()
2000 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, in evergreen_emit_polygon_offset()
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Dr600_state_common.c88 radeon_set_context_reg(cs, R_028410_SX_ALPHA_TEST_CONTROL, in r600_emit_alphatest_state()
91 radeon_set_context_reg(cs, R_028438_SX_ALPHA_REF, alpha_ref); in r600_emit_alphatest_state()
259 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, a->vgt_multi_prim_ib_reset_en); in r600_emit_vgt_state()
1868 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL, in r600_emit_clip_misc_state()
1872 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL, in r600_emit_clip_misc_state()
1878 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF, in r600_emit_clip_misc_state()
1902 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE, in r600_emit_rasterizer_prim_state()
2091 radeon_set_context_reg(cs, CM_R_028AA8_IA_MULTI_VGT_PARAM, in r600_draw_vbo()
2121 radeon_set_context_reg(cs, R_028814_PA_SU_SC_MODE_CNTL, su_sc_mode_cntl); in r600_draw_vbo()
2217 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, t->stride_in_dw); in r600_draw_vbo()
Dr600_cs.h153 static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) in radeon_set_context_reg() function
Dr600_hw_context.c281 radeon_set_context_reg(cs, R_028350_SX_MISC, 0); in r600_context_gfx_flush()
Dr600_pipe.h992 radeon_set_context_reg(cs, reg, value); in radeon_set_context_reg_flag()
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state_msaa.c134 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, 0); in si_emit_sample_locations()
135 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, 0); in si_emit_sample_locations()
136 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, 0); in si_emit_sample_locations()
137 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, 0); in si_emit_sample_locations()
140 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]); in si_emit_sample_locations()
141 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]); in si_emit_sample_locations()
142 radeon_set_context_reg(cs, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]); in si_emit_sample_locations()
143 radeon_set_context_reg(cs, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]); in si_emit_sample_locations()
146 radeon_set_context_reg(cs, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]); in si_emit_sample_locations()
147 radeon_set_context_reg(cs, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]); in si_emit_sample_locations()
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Dsi_state_binning.c331 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0, in si_emit_dpbb_disable()
334 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL, in si_emit_dpbb_disable()
435 radeon_set_context_reg(cs, R_028C44_PA_SC_BINNER_CNTL_0, in si_emit_dpbb_state()
446 radeon_set_context_reg(cs, R_028060_DB_DFSM_CONTROL, in si_emit_dpbb_state()
Dsi_state_draw.c308 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, in si_emit_derived_tess_state()
552 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE, in si_emit_rasterizer_prim_state()
602 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param); in si_emit_draw_registers()
616 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim); in si_emit_draw_registers()
626 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, in si_emit_draw_registers()
635 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, in si_emit_draw_registers()
660 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE, in si_emit_draw_packets()
Dsi_state.c110 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask); in si_emit_cb_render_state()
134 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL, in si_emit_cb_render_state()
797 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL, in si_emit_clip_regs()
802 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL, in si_emit_clip_regs()
1427 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, in si_emit_db_render_state()
1448 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL, in si_emit_db_render_state()
2977 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, in si_emit_framebuffer_state()
3063 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4, in si_emit_framebuffer_state()
3126 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0); in si_emit_framebuffer_state()
3162 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base); in si_emit_framebuffer_state()
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Dsi_state_streamout.c346 radeon_set_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 + 16*i, 0); in si_emit_streamout_end()
Dsi_state_shaders.c3393 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE, in si_emit_scratch_state()
/external/mesa3d/src/amd/vulkan/
Dsi_cmd_buffer.c158 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, raster_config_se); in si_write_harvested_raster_configs()
160 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1); in si_write_harvested_raster_configs()
320 radeon_set_context_reg(cs, R_028350_PA_SC_RASTER_CONFIG, in si_set_raster_config()
323 radeon_set_context_reg(cs, R_028354_PA_SC_RASTER_CONFIG_1, in si_set_raster_config()
354 radeon_set_context_reg(cs, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64)); in si_emit_config()
356 radeon_set_context_reg(cs, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0)); in si_emit_config()
360 radeon_set_context_reg(cs, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES); in si_emit_config()
361 radeon_set_context_reg(cs, R_028A58_VGT_ES_PER_GS, 0x40); in si_emit_config()
365 radeon_set_context_reg(cs, R_028A5C_VGT_GS_PER_VS, 0x2); in si_emit_config()
366 radeon_set_context_reg(cs, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0); in si_emit_config()
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Dradv_cmd_buffer.c527 …radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, pipeline->graphics.blend.cb_colo… in radv_emit_graphics_blend_state()
528 …radeon_set_context_reg(cmd_buffer->cs, R_028B70_DB_ALPHA_TO_MASK, pipeline->graphics.blend.db_alph… in radv_emit_graphics_blend_state()
547 radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, ds->db_depth_control); in radv_emit_graphics_depth_stencil_state()
548 radeon_set_context_reg(cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL, ds->db_stencil_control); in radv_emit_graphics_depth_stencil_state()
550 radeon_set_context_reg(cmd_buffer->cs, R_028000_DB_RENDER_CONTROL, ds->db_render_control); in radv_emit_graphics_depth_stencil_state()
551 radeon_set_context_reg(cmd_buffer->cs, R_028010_DB_RENDER_OVERRIDE2, ds->db_render_override2); in radv_emit_graphics_depth_stencil_state()
604 radeon_set_context_reg(cmd_buffer->cs, R_028804_DB_EQAA, ms->db_eqaa); in radv_update_multisample_state()
605 radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1); in radv_update_multisample_state()
644 radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0); in radv_update_multisample_state()
661 radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL, in radv_emit_graphics_raster_state()
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Dradv_cs.h66 static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) in radeon_set_context_reg() function
/external/mesa3d/src/gallium/drivers/radeon/
Dr600_cs.h136 static inline void radeon_set_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) in radeon_set_context_reg() function