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Searched refs:radeon_set_sh_reg (Results 1 – 7 of 7) sorted by relevance

/external/mesa3d/src/amd/vulkan/
Dsi_cmd_buffer.c210 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID, in si_emit_compute()
438 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, in si_emit_config()
441 radeon_set_sh_reg(cs, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, in si_emit_config()
443 radeon_set_sh_reg(cs, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, in si_emit_config()
445 radeon_set_sh_reg(cs, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, in si_emit_config()
455 radeon_set_sh_reg(cs, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, in si_emit_config()
466 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, in si_emit_config()
468 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2)); in si_emit_config()
475 radeon_set_sh_reg(cs, R_00B118_SPI_SHADER_PGM_RSRC3_VS, in si_emit_config()
477 radeon_set_sh_reg(cs, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31)); in si_emit_config()
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Dradv_cs.h93 static inline void radeon_set_sh_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) in radeon_set_sh_reg() function
Dradv_cmd_buffer.c633 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, offset); in radv_update_multisample_state()
787 radeon_set_sh_reg(cmd_buffer->cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2); in radv_emit_hw_ls()
892 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, in radv_emit_tess_shaders()
902 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, in radv_emit_tess_shaders()
2659 radeon_set_sh_reg(cmd_buffer->cs, R_00B860_COMPUTE_TMPRING_SIZE, in radv_emit_compute_pipeline()
2684 radeon_set_sh_reg(cmd_buffer->cs, R_00B854_COMPUTE_RESOURCE_LIMITS, in radv_emit_compute_pipeline()
3168 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index); in radv_emit_view_index()
3175 radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index); in radv_emit_view_index()
/external/mesa3d/src/gallium/drivers/radeon/
Dr600_cs.h161 static inline void radeon_set_sh_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) in radeon_set_sh_reg() function
/external/mesa3d/src/gallium/drivers/r600/
Dr600_cs.h178 static inline void radeon_set_sh_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value) in radeon_set_sh_reg() function
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_compute.c306 radeon_set_sh_reg(cs, R_00B82C_COMPUTE_MAX_WAVE_ID, in si_initialize_compute()
462 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE, in si_switch_compute_shader()
742 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS, in si_emit_dispatch_packets()
Dsi_state_draw.c263 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2); in si_emit_derived_tess_state()
281 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2); in si_emit_derived_tess_state()
575 radeon_set_sh_reg(cs, in si_emit_vs_state()