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Searched refs:radeon_set_sh_reg_seq (Results 1 – 8 of 8) sorted by relevance

/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_compute.c282 radeon_set_sh_reg_seq(cs, R_00B858_COMPUTE_STATIC_THREAD_MGMT_SE0, 2); in si_initialize_compute()
289 radeon_set_sh_reg_seq(cs, in si_initialize_compute()
451 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2); in si_switch_compute_shader()
455 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2); in si_switch_compute_shader()
509 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + in setup_scratch_rsrc_user_sgprs()
577 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + in si_setup_user_sgprs_co_v2()
589 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0 + in si_setup_user_sgprs_co_v2()
599 radeon_set_sh_reg_seq(cs, in si_setup_user_sgprs_co_v2()
661 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2); in si_upload_compute_input()
705 radeon_set_sh_reg_seq(cs, grid_size_reg, 3); in si_setup_tgsi_grid()
[all …]
Dsi_state_draw.c266 radeon_set_sh_reg_seq(cs, in si_emit_derived_tess_state()
282 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2); in si_emit_derived_tess_state()
287 radeon_set_sh_reg_seq(cs, in si_emit_derived_tess_state()
296 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2); in si_emit_derived_tess_state()
809 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4, in si_emit_draw_packets()
818 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3); in si_emit_draw_packets()
/external/mesa3d/src/amd/vulkan/
Dradv_cs.h84 static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) in radeon_set_sh_reg_seq() function
95 radeon_set_sh_reg_seq(cs, reg, 1); in radeon_set_sh_reg()
Dradv_cmd_buffer.c587 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 2); in radv_emit_userdata_address()
738 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4); in radv_emit_hw_vs()
766 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4); in radv_emit_hw_es()
780 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2); in radv_emit_hw_ls()
789 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2); in radv_emit_hw_ls()
801 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2); in radv_emit_hw_hs()
805 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2); in radv_emit_hw_hs()
810 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4); in radv_emit_hw_hs()
878 radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, 4); in radv_emit_tess_shaders()
949 radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2); in radv_emit_geometry_shader()
[all …]
Dsi_cmd_buffer.c179 radeon_set_sh_reg_seq(cs, R_00B810_COMPUTE_START_X, 3); in si_emit_compute()
184 radeon_set_sh_reg_seq(cs, R_00B854_COMPUTE_RESOURCE_LIMITS, in si_emit_compute()
193 radeon_set_sh_reg_seq(cs, in si_emit_compute()
Dradv_device.c1742 radeon_set_sh_reg_seq(cs, regs[i], 2); in radv_get_preamble_cs()
1755 radeon_set_sh_reg_seq(cs, regs[i], 2); in radv_get_preamble_cs()
1769 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2); in radv_get_preamble_cs()
/external/mesa3d/src/gallium/drivers/radeon/
Dr600_cs.h153 static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) in radeon_set_sh_reg_seq() function
163 radeon_set_sh_reg_seq(cs, reg, 1); in radeon_set_sh_reg()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_cs.h170 static inline void radeon_set_sh_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num) in radeon_set_sh_reg_seq() function
180 radeon_set_sh_reg_seq(cs, reg, 1); in radeon_set_sh_reg()