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Searched refs:rcl (Results 1 – 22 of 22) sorted by relevance

/external/mesa3d/src/gallium/drivers/vc5/
Dvc5_rcl.c417 cl_emit(&job->rcl, START_ADDRESS_OF_GENERIC_TILE_LIST, branch) { in vc5_rcl_emit_generic_per_tile_list()
444 assert(!job->rcl.bo); in v3dX()
446 vc5_cl_ensure_space_with_branch(&job->rcl, 200 + 256 * in v3dX()
448 job->submit.rcl_start = job->rcl.bo->offset; in v3dX()
449 vc5_job_add_bo(job, job->rcl.bo); in v3dX()
461 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_COMMON_CONFIGURATION, in v3dX()
515 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_RENDER_TARGET_CONFIG, rt) { in v3dX()
529 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART1, in v3dX()
537 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART2, in v3dX()
550 cl_emit(&job->rcl, TILE_RENDERING_MODE_CONFIGURATION_CLEAR_COLORS_PART3, in v3dX()
[all …]
Dvc5_job.c84 vc5_destroy_cl(&job->rcl); in vc5_job_free()
100 vc5_init_cl(job, &job->rcl); in vc5_job_create()
421 job->submit.rcl_end = job->rcl.bo->offset + cl_offset(&job->rcl); in vc5_job_submit()
Dvc5_context.h203 struct vc5_cl rcl; member
/external/mesa3d/src/gallium/drivers/vc4/kernel/
Dvc4_render_cl.c45 struct drm_gem_cma_object *rcl; member
51 *(u8 *)(setup->rcl->vaddr + setup->next_offset) = val; in rcl_u8()
57 *(u16 *)(setup->rcl->vaddr + setup->next_offset) = val; in rcl_u16()
63 *(u32 *)(setup->rcl->vaddr + setup->next_offset) = val; in rcl_u32()
326 setup->rcl = drm_gem_cma_create(dev, size); in vc4_create_rcl_bo()
327 if (!setup->rcl) in vc4_create_rcl_bo()
329 list_addtail(&to_vc4_bo(&setup->rcl->base)->unref_head, in vc4_create_rcl_bo()
372 exec->ct1ca = setup->rcl->paddr; in vc4_create_rcl_bo()
373 exec->ct1ea = setup->rcl->paddr + setup->next_offset; in vc4_create_rcl_bo()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrShiftRotate.td293 "rcl{b}\t$dst", []>;
295 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
298 "rcl{b}\t{%cl, $dst|$dst, CL}", []>;
301 "rcl{w}\t$dst", []>, OpSize;
303 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize;
306 "rcl{w}\t{%cl, $dst|$dst, CL}", []>, OpSize;
309 "rcl{l}\t$dst", []>;
311 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>;
314 "rcl{l}\t{%cl, $dst|$dst, CL}", []>;
318 "rcl{q}\t$dst", []>;
[all …]
DX86InstrInfo.td1778 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
DX86GenAsmWriter1.inc3937 "hf\000pushfd\000pushfq\000push\tFS\000push\tGS\000push\tSS\000rcl\t\000"
/external/llvm/lib/Target/X86/
DX86InstrShiftRotate.td344 "rcl{b}\t$dst", [], IIC_SR>;
346 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
349 "rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
352 "rcl{w}\t$dst", [], IIC_SR>, OpSize16;
354 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
357 "rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
360 "rcl{l}\t$dst", [], IIC_SR>, OpSize32;
362 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
365 "rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
369 "rcl{q}\t$dst", [], IIC_SR>;
[all …]
DX86InstrInfo.td3041 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrShiftRotate.td332 "rcl{b}\t{%cl, $dst|$dst, cl}", []>;
334 "rcl{w}\t{%cl, $dst|$dst, cl}", []>, OpSize16;
336 "rcl{l}\t{%cl, $dst|$dst, cl}", []>, OpSize32;
338 "rcl{q}\t{%cl, $dst|$dst, cl}", []>;
343 "rcl{b}\t$dst", []>;
345 "rcl{b}\t{$cnt, $dst|$dst, $cnt}", []>;
347 "rcl{w}\t$dst", []>, OpSize16;
349 "rcl{w}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize16;
351 "rcl{l}\t$dst", []>, OpSize32;
353 "rcl{l}\t{$cnt, $dst|$dst, $cnt}", []>, OpSize32;
[all …]
DX86InstrInfo.td3432 defm : ShiftRotateByOneAlias<"rcl", "RCL">;
/external/swiftshader/third_party/LLVM/test/MC/X86/
Dx86-64.s332 rcl %bl label
/external/llvm/test/MC/X86/
Dx86-64.s356 rcl %bl label
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/X86/
Dx86-64.s352 rcl %bl label
/external/elfutils/libcpu/defs/
Di386483 1101000{w},{mod}010{r_m}:rcl{w} {mod}{r_m}{w}
484 1101001{w},{mod}010{r_m}:rcl{w} %cl,{mod}{r_m}{w}
485 1100000{w},{mod}010{r_m},{imm8}:rcl{w} {imm8},{mod}{r_m}{w}
/external/mesa3d/src/mesa/x86/
Dassyntax.h582 #define RCL_L(a, b) CHOICE(rcll ARG2(a,b), rcll ARG2(a,b), _LTOG rcl ARG2(b,a))
583 #define RCL_W(a, b) CHOICE(rclw ARG2(a,b), rclw ARG2(a,b), _WTOG rcl ARG2(b,a))
1294 #define RCL_L(a, b) rcl L_(b), L_(a)
1295 #define RCL_W(a, b) rcl W_(b), W_(a)
1296 #define RCL_B(a, b) rcl B_(b), B_(a)
/external/v8/src/ia32/
Dassembler-ia32.h732 void rcl(Register dst, uint8_t imm8);
Dassembler-ia32.cc1117 void Assembler::rcl(Register dst, uint8_t imm8) { in rcl() function in v8::internal::Assembler
/external/v8/src/x64/
Dassembler-x64.h395 V(rcl, 0x2) \
/external/elfutils/tests/
Dtestfile44.expect.bz21testfile44.o: elf32-elf_i386 2 3Disassembly of section .text: 4 5 0 ...
Dtestfile45.expect.bz21testfile45.o: elf64-elf_x86_64 2 3Disassembly of section .text: 4 5 0 ...
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenAsmMatcher.inc6651 "hl\005pushq\005pushw\004pxor\003rcl\004rclb\004rcll\004rclq\004rclw\005"
23426 { 6592 /* rcl */, X86::RCL16r1, Convert__Reg1_0__Tie0_1_1, 0, { MCK_GR16 }, },
23427 { 6592 /* rcl */, X86::RCL32r1, Convert__Reg1_0__Tie0_1_1, 0, { MCK_GR32 }, },
23428 { 6592 /* rcl */, X86::RCL64r1, Convert__Reg1_0__Tie0_1_1, 0, { MCK_GR64 }, },
23429 { 6592 /* rcl */, X86::RCL8r1, Convert__Reg1_0__Tie0_1_1, 0, { MCK_GR8 }, },
23430 { 6592 /* rcl */, X86::RCL16m1, Convert__Mem165_0, 0, { MCK_Mem16 }, },
23431 { 6592 /* rcl */, X86::RCL32m1, Convert__Mem325_0, 0, { MCK_Mem32 }, },
23432 { 6592 /* rcl */, X86::RCL64m1, Convert__Mem645_0, Feature_In64BitMode, { MCK_Mem64 }, },
23433 { 6592 /* rcl */, X86::RCL8m1, Convert__Mem85_0, 0, { MCK_Mem8 }, },
23434 { 6592 /* rcl */, X86::RCL16rCL, Convert__Reg1_0__Tie0_1_1, 0, { MCK_GR16, MCK_CL }, },
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