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Searched refs:rcwsr (Results 1 – 25 of 68) sorted by relevance

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/external/u-boot/arch/powerpc/cpu/mpc85xx/
Dfsl_corenet_serdes.c127 return !(in_be32(&gur->rcwsr[word]) & (0x80000000 >> bit)); in serdes_lane_enabled()
135 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) in is_serdes_configured()
171 if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) in serdes_get_first_lane()
174 prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; in serdes_get_first_lane()
253 if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) in serdes_reset_rx()
257 prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; in serdes_reset_rx()
297 rcw5 = in_be32(gur->rcwsr + 5); in enable_bank()
384 srds_ratio_b2 = (in_be32(&gur->rcwsr[4]) >> 13) & 7; in p4080_erratum_serdes8()
523 if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) in fsl_serdes_init()
527 cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; in fsl_serdes_init()
[all …]
Dspeed.c95 ddr_refclk_sel = (in_be32(&gur->rcwsr[5]) >> in get_sys_info()
112 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; in get_sys_info()
113 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> in get_sys_info()
118 mem_pll_rat = (in_be32(&gur->rcwsr[0]) >> in get_sys_info()
214 rcw_tmp = in_be32(&gur->rcwsr[15]) - 4; in get_sys_info()
216 rcw_tmp = in_be32(&gur->rcwsr[7]); in get_sys_info()
267 rcw_tmp1 = in_be32(&gur->rcwsr[7]); /* Reading RCW bits: 224-255*/ in get_sys_info()
268 rcw_tmp2 = in_be32(&gur->rcwsr[15]); /* Reading RCW bits: 480-511*/ in get_sys_info()
416 rcw_tmp = in_be32(&gur->rcwsr[15]); in get_sys_info()
462 rcw_tmp = in_be32(&gur->rcwsr[ESDHC_CLK_RCWSR]); in get_sys_info()
[all …]
Dcpu.c61 u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC) in checkcpu()
277 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { in checkcpu()
278 u32 rcw = in_be32(&gur->rcwsr[i]); in checkcpu()
/external/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
Dfsl_lsch3_serdes.c73 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]); in serdes_get_first_lane()
80 cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]); in serdes_get_first_lane()
104 void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, in serdes_init() argument
116 cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask; in serdes_init()
338 u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]); in setup_serdes_volt()
342 u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]); in setup_serdes_volt()
Dfsl_lsch2_speed.c65 sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> in get_sys_info()
72 sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> in get_sys_info()
98 rcw_tmp = in_be32(&gur->rcwsr[7]); in get_sys_info()
128 rcw_tmp = in_be32(&gur->rcwsr[15]); in get_sys_info()
Dfsl_lsch3_speed.c87 sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >> in get_sys_info()
90 sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >> in get_sys_info()
95 sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >> in get_sys_info()
Dfsl_lsch2_serdes.c42 u32 cfg = gur_in32(&gur->rcwsr[4]); in serdes_get_first_lane()
78 u32 cfg = gur_in32(&gur->rcwsr[4]) & in get_serdes_protocol()
111 cfg = gur_in32(&gur->rcwsr[4]) & sd_prctl_mask; in serdes_init()
148 u32 cfg_rcw4 = gur_in32(&gur->rcwsr[4]); in setup_serdes_volt()
149 u32 cfg_rcw5 = gur_in32(&gur->rcwsr[5]); in setup_serdes_volt()
/external/u-boot/board/freescale/b4860qds/
Deth_b4860qds.c61 serdes2_prtcl = in_be32(&gur->rcwsr[4]) & in initialize_lane_to_slot()
159 serdes1_prtcl = in_be32(&gur->rcwsr[4]) & in board_eth_init()
168 serdes2_prtcl = in_be32(&gur->rcwsr[4]) & in board_eth_init()
369 u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; in board_ft_fman_fixup_port()
/external/u-boot/board/freescale/ls2080aqds/
Deth.c443 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & in initialize_dpmac_to_slot()
446 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) & in initialize_dpmac_to_slot()
597 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & in ls2080a_handle_phy_interface_sgmii()
600 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) & in ls2080a_handle_phy_interface_sgmii()
740 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & in ls2080a_handle_phy_interface_qsgmii()
805 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & in ls2080a_handle_phy_interface_xsgmii()
839 int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & in board_eth_init()
842 int serdes2_prtcl = (in_le32(&gur->rcwsr[28]) & in board_eth_init()
/external/u-boot/drivers/net/ldpaa_eth/
Dls1088a.c96 ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC1_REGSR - 1]) in fsl_rgmii_init()
105 ec = gur_in32(&gur->rcwsr[FSL_CHASSIS3_EC2_REGSR - 1]) in fsl_rgmii_init()
/external/u-boot/board/freescale/ls1046ardb/
Deth.c25 srds_s1 = in_be32(&gur->rcwsr[4]) & in board_eth_init()
87 srds_s1 = in_be32(&gur->rcwsr[4]) & in fdt_update_ethernet_dt()
/external/u-boot/arch/arm/cpu/armv7/ls102xa/
Dfsl_ls1_serdes.c43 u32 cfg = in_be32(&gur->rcwsr[4]); in serdes_get_first_lane()
82 cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask; in serdes_init()
Dclock.c49 sys_info->freq_systembus *= (in_be32(&gur->rcwsr[0]) >> in get_sys_info()
51 sys_info->freq_ddrbus *= (in_be32(&gur->rcwsr[0]) >> in get_sys_info()
Dcpu.c277 for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) { in print_cpuinfo()
278 u32 rcw = in_be32(&gur->rcwsr[i]); in print_cpuinfo()
/external/u-boot/board/freescale/ls1088a/
Deth_ls1088aqds.c417 cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & in initialize_dpmac_to_slot()
470 cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & in ls1088a_handle_phy_interface_sgmii()
522 cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & in ls1088a_handle_phy_interface_qsgmii()
561 cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & in ls1088a_handle_phy_interface_xsgmii()
586 cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & in ls1088a_handle_phy_interface_rgmii()
/external/u-boot/board/freescale/t4rdb/
Deth.c47 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & in board_eth_init()
50 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & in board_eth_init()
Dspl.c58 plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f; in board_init_f()
/external/u-boot/board/freescale/t4qds/
Dt4240qds.c351 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & in config_frontside_crossbar_vsc3316()
383 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & in config_frontside_crossbar_vsc3316()
430 srds_prtcl_s3 = in_be32(&gur->rcwsr[4]) & in config_backside_crossbar_mux()
475 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) & in config_backside_crossbar_mux()
Deth.c177 u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; in board_ft_fman_fixup_port()
346 u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL; in fdt_fixup_board_enet()
495 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & in board_eth_init()
498 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & in board_eth_init()
/external/u-boot/board/freescale/t208xqds/
Dt208xqds.c98 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & in brd_mux_lane_to_slot()
102 u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) & in brd_mux_lane_to_slot()
Deth_t208xqds.c211 u32 srds_s1 = in_be32(&gur->rcwsr[4]) & in board_ft_fman_fixup_port()
450 u32 srds_s1 = in_be32(&gur->rcwsr[4]) & in initialize_lane_to_slot()
520 u32 rcwsr13 = in_be32(&gur->rcwsr[13]); in board_eth_init()
523 srds_s1 = in_be32(&gur->rcwsr[4]) & in board_eth_init()
/external/u-boot/board/freescale/t102xrdb/
Dt102xrdb.c49 srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; in checkboard()
100 srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & in board_mux_lane()
/external/u-boot/drivers/net/fm/
Dt1040.c15 u32 rcwsr13 = in_be32(&gur->rcwsr[13]); in fman_port_enet_if()
/external/u-boot/board/freescale/ls1043ardb/
Deth.c25 srds_s1 = in_be32(&gur->rcwsr[4]) & in board_eth_init()
/external/u-boot/board/freescale/t208xrdb/
Deth_t208xrdb.c36 srds_s1 = in_be32(&gur->rcwsr[4]) & in board_eth_init()

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