Searched refs:rdgr0 (Results 1 – 2 of 2) sorted by relevance
28 u32 rdgr0; /* 0x5c rank dqs gating register */ member
372 u32 dgr = readl(rank == 0 ? &dram->rdgr0 : &dram->rdgr1); in mctl_set_dqs_gating_delay()381 writel(dgr, rank == 0 ? &dram->rdgr0 : &dram->rdgr1); in mctl_set_dqs_gating_delay()