Searched refs:ref_clk_satr (Results 1 – 1 of 1) sorted by relevance
388 u32 reg, ref_clk_satr; in mv_ddr_sar_freq_get() local395 ref_clk_satr = reg_read(DEVICE_SAMPLE_AT_RESET2_REG); in mv_ddr_sar_freq_get()396 if (((ref_clk_satr >> DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET) & 0x1) == in mv_ddr_sar_freq_get()482 u32 reg, ref_clk_satr; in ddr3_tip_a38x_get_medium_freq() local489 ref_clk_satr = reg_read(DEVICE_SAMPLE_AT_RESET2_REG); in ddr3_tip_a38x_get_medium_freq()490 if (((ref_clk_satr >> DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET) & 0x1) == in ddr3_tip_a38x_get_medium_freq()740 u32 sar_val, ref_clk_satr; in ddr3_tip_a38x_set_divider() local755 ref_clk_satr = reg_read(DEVICE_SAMPLE_AT_RESET2_REG); in ddr3_tip_a38x_set_divider()756 if (((ref_clk_satr >> DEVICE_SAMPLE_AT_RESET2_REG_REFCLK_OFFSET) & 0x1) == in ddr3_tip_a38x_set_divider()