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/external/libvpx/libvpx/vpx_dsp/mips/
Didct32x32_msa.c44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
58 DOTP_CONST_PAIR(reg0, reg4, cospi_16_64, cospi_16_64, reg0, reg4); in idct32x8_row_even_process_store()
60 BUTTERFLY_4(reg4, reg0, reg2, reg6, vec1, vec3, vec2, vec0); in idct32x8_row_even_process_store()
65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
66 DOTP_CONST_PAIR(reg0, reg7, cospi_30_64, cospi_2_64, reg0, reg7); in idct32x8_row_even_process_store()
71 vec0 = reg0 + reg4; in idct32x8_row_even_process_store()
72 reg0 = reg0 - reg4; in idct32x8_row_even_process_store()
87 DOTP_CONST_PAIR(reg7, reg0, cospi_24_64, cospi_8_64, reg0, reg7); in idct32x8_row_even_process_store()
90 vec0 = reg0 - reg6; in idct32x8_row_even_process_store()
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
D2010-05-12-FastAllocKills.ll9 ; %reg1025<def> = MUL_Fp80m32 %reg1024, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
18 ; %FP0<def> = LD_Fp80m <fi#3>, 1, %reg0, 0, %reg0; mem:LD10[FixedStack3](align=4)
20 ; %FP2<def> = MUL_Fp80m32 %FP1, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
22 ; ST_FpP80m <fi#3>, 1, %reg0, 0, %reg0, %FP0<kill>; mem:ST10[FixedStack3](align=4)
23 ; ST_FpP80m <fi#4>, 1, %reg0, 0, %reg0, %FP1<kill>; mem:ST10[FixedStack4](align=4)
24 ; ST_FpP80m <fi#5>, 1, %reg0, 0, %reg0, %FP2<kill>; mem:ST10[FixedStack5](align=4)
/external/llvm/test/CodeGen/X86/
D2010-05-12-FastAllocKills.ll9 ; %reg1025<def> = MUL_Fp80m32 %reg1024, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
18 ; %FP0<def> = LD_Fp80m <fi#3>, 1, %reg0, 0, %reg0; mem:LD10[FixedStack3](align=4)
20 ; %FP2<def> = MUL_Fp80m32 %FP1, %RIP, 1, %reg0, <cp#0>, %reg0; mem:LD4[ConstantPool]
22 ; ST_FpP80m <fi#3>, 1, %reg0, 0, %reg0, %FP0<kill>; mem:ST10[FixedStack3](align=4)
23 ; ST_FpP80m <fi#4>, 1, %reg0, 0, %reg0, %FP1<kill>; mem:ST10[FixedStack4](align=4)
24 ; ST_FpP80m <fi#5>, 1, %reg0, 0, %reg0, %FP2<kill>; mem:ST10[FixedStack5](align=4)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
D2010-05-12-FastAllocKills.ll10 ; %reg1025 = MUL_Fp80m32 %reg1024, %rip, 1, %reg0, %const.0, %reg0; mem:LD4[ConstantPool]
19 ; %fp0 = LD_Fp80m %stack.3, 1, %reg0, 0, %reg0; mem:LD10[FixedStack3](align=4)
21 ; %fp2 = MUL_Fp80m32 %fp1, %rip, 1, %reg0, %const.0, %reg0; mem:LD4[ConstantPool]
23 ; ST_FpP80m %stack.3, 1, %reg0, 0, %reg0, killed %fp0; mem:ST10[FixedStack3](align=4)
24 ; ST_FpP80m %stack.4, 1, %reg0, 0, %reg0, killed %fp1; mem:ST10[FixedStack4](align=4)
25 ; ST_FpP80m %stack.5, 1, %reg0, 0, %reg0, killed %fp2; mem:ST10[FixedStack5](align=4)
/external/u-boot/post/lib_powerpc/
Dtwo.c81 unsigned int reg0 = (reg + 0) % 32; in cpu_post_test_two() local
89 ASM_STW(reg0, stk, 4), in cpu_post_test_two()
91 ASM_LWZ(reg0, stk, 8), in cpu_post_test_two()
92 ASM_11(test->cmd, reg1, reg0), in cpu_post_test_two()
95 ASM_LWZ(reg0, stk, 4), in cpu_post_test_two()
106 ASM_STW(reg0, stk, 4), in cpu_post_test_two()
108 ASM_LWZ(reg0, stk, 8), in cpu_post_test_two()
109 ASM_11(test->cmd, reg1, reg0) | BIT_C, in cpu_post_test_two()
112 ASM_LWZ(reg0, stk, 4), in cpu_post_test_two()
Dtwox.c81 unsigned int reg0 = (reg + 0) % 32; in cpu_post_test_twox() local
89 ASM_STW(reg0, stk, 4), in cpu_post_test_twox()
91 ASM_LWZ(reg0, stk, 8), in cpu_post_test_twox()
92 ASM_11X(test->cmd, reg1, reg0), in cpu_post_test_twox()
95 ASM_LWZ(reg0, stk, 4), in cpu_post_test_twox()
106 ASM_STW(reg0, stk, 4), in cpu_post_test_twox()
108 ASM_LWZ(reg0, stk, 8), in cpu_post_test_twox()
109 ASM_11X(test->cmd, reg1, reg0) | BIT_C, in cpu_post_test_twox()
112 ASM_LWZ(reg0, stk, 4), in cpu_post_test_twox()
Dsrawi.c61 unsigned int reg0 = (reg + 0) % 32; in cpu_post_test_srawi() local
69 ASM_STW(reg0, stk, 4), in cpu_post_test_srawi()
71 ASM_LWZ(reg0, stk, 8), in cpu_post_test_srawi()
72 ASM_11S(test->cmd, reg1, reg0, test->op2), in cpu_post_test_srawi()
75 ASM_LWZ(reg0, stk, 4), in cpu_post_test_srawi()
86 ASM_STW(reg0, stk, 4), in cpu_post_test_srawi()
88 ASM_LWZ(reg0, stk, 8), in cpu_post_test_srawi()
89 ASM_11S(test->cmd, reg1, reg0, test->op2) | BIT_C, in cpu_post_test_srawi()
92 ASM_LWZ(reg0, stk, 4), in cpu_post_test_srawi()
Drlwinm.c59 unsigned int reg0 = (reg + 0) % 32; in cpu_post_test_rlwinm() local
67 ASM_STW(reg0, stk, 4), in cpu_post_test_rlwinm()
69 ASM_LWZ(reg0, stk, 8), in cpu_post_test_rlwinm()
70 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me), in cpu_post_test_rlwinm()
73 ASM_LWZ(reg0, stk, 4), in cpu_post_test_rlwinm()
84 ASM_STW(reg0, stk, 4), in cpu_post_test_rlwinm()
86 ASM_LWZ(reg0, stk, 8), in cpu_post_test_rlwinm()
87 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, in cpu_post_test_rlwinm()
91 ASM_LWZ(reg0, stk, 4), in cpu_post_test_rlwinm()
Drlwnm.c60 unsigned int reg0 = (reg + 0) % 32; in cpu_post_test_rlwnm() local
70 ASM_STW(reg0, stk, 8), in cpu_post_test_rlwnm()
74 ASM_LWZ(reg0, stk, 16), in cpu_post_test_rlwnm()
75 ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me), in cpu_post_test_rlwnm()
79 ASM_LWZ(reg0, stk, 8), in cpu_post_test_rlwnm()
91 ASM_STW(reg0, stk, 8), in cpu_post_test_rlwnm()
95 ASM_LWZ(reg0, stk, 16), in cpu_post_test_rlwnm()
96 ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me) | in cpu_post_test_rlwnm()
101 ASM_LWZ(reg0, stk, 8), in cpu_post_test_rlwnm()
Drlwimi.c62 unsigned int reg0 = (reg + 0) % 32; in cpu_post_test_rlwimi() local
71 ASM_STW(reg0, stk, 4), in cpu_post_test_rlwimi()
74 ASM_LWZ(reg0, stk, 12), in cpu_post_test_rlwimi()
75 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me), in cpu_post_test_rlwimi()
78 ASM_LWZ(reg0, stk, 4), in cpu_post_test_rlwimi()
90 ASM_STW(reg0, stk, 4), in cpu_post_test_rlwimi()
93 ASM_LWZ(reg0, stk, 12), in cpu_post_test_rlwimi()
94 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me) | in cpu_post_test_rlwimi()
98 ASM_LWZ(reg0, stk, 4), in cpu_post_test_rlwimi()
Dthreex.c125 unsigned int reg0 = (reg + 0) % 32; in cpu_post_test_threex() local
135 ASM_STW(reg0, stk, 8), in cpu_post_test_threex()
139 ASM_LWZ(reg0, stk, 16), in cpu_post_test_threex()
140 ASM_12X(test->cmd, reg2, reg1, reg0), in cpu_post_test_threex()
144 ASM_LWZ(reg0, stk, 8), in cpu_post_test_threex()
156 ASM_STW(reg0, stk, 8), in cpu_post_test_threex()
160 ASM_LWZ(reg0, stk, 16), in cpu_post_test_threex()
161 ASM_12X(test->cmd, reg2, reg1, reg0) | BIT_C, in cpu_post_test_threex()
165 ASM_LWZ(reg0, stk, 8), in cpu_post_test_threex()
Dthree.c155 unsigned int reg0 = (reg + 0) % 32; in cpu_post_test_three() local
165 ASM_STW(reg0, stk, 8), in cpu_post_test_three()
169 ASM_LWZ(reg0, stk, 16), in cpu_post_test_three()
170 ASM_12(test->cmd, reg2, reg1, reg0), in cpu_post_test_three()
174 ASM_LWZ(reg0, stk, 8), in cpu_post_test_three()
186 ASM_STW(reg0, stk, 8), in cpu_post_test_three()
190 ASM_LWZ(reg0, stk, 16), in cpu_post_test_three()
191 ASM_12(test->cmd, reg2, reg1, reg0) | BIT_C, in cpu_post_test_three()
195 ASM_LWZ(reg0, stk, 8), in cpu_post_test_three()
Dandi.c61 unsigned int reg0 = (reg + 0) % 32; in cpu_post_test_andi() local
69 ASM_STW(reg0, stk, 4), in cpu_post_test_andi()
71 ASM_LWZ(reg0, stk, 8), in cpu_post_test_andi()
72 ASM_11IX(test->cmd, reg1, reg0, test->op2), in cpu_post_test_andi()
75 ASM_LWZ(reg0, stk, 4), in cpu_post_test_andi()
Dthreei.c75 unsigned int reg0 = (reg + 0) % 32; in cpu_post_test_threei() local
83 ASM_STW(reg0, stk, 4), in cpu_post_test_threei()
85 ASM_LWZ(reg0, stk, 8), in cpu_post_test_threei()
86 ASM_11IX(test->cmd, reg1, reg0, test->op2), in cpu_post_test_threei()
89 ASM_LWZ(reg0, stk, 4), in cpu_post_test_threei()
/external/elfutils/tests/
Drun-varlocs.sh71 [400524,400528) {reg0}
74 [40052e,400531) {reg0}
153 [401053,40105f) {reg0}
174 [4011d3,4011df) {reg0}
184 [401193,40119b) {reg0}
185 [4011a7,4011b4) {reg0}
188 [4011a7,4011b4) {reg0}
191 [40119b,4011a6) {reg0}
193 [4011b4,4011bf) {reg0}
231 [401053,40105f) {reg0}
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
D2011-11-29-128bitArithmetics.ll32 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
33 ; CHECK: movt [[reg0]], :upper16:{{.*}}
63 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
64 ; CHECK: movt [[reg0]], :upper16:{{.*}}
94 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
95 ; CHECK: movt [[reg0]], :upper16:{{.*}}
125 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
126 ; CHECK: movt [[reg0]], :upper16:{{.*}}
156 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
157 ; CHECK: movt [[reg0]], :upper16:{{.*}}
[all …]
/external/llvm/test/CodeGen/ARM/
D2011-11-29-128bitArithmetics.ll32 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
33 ; CHECK: movt [[reg0]], :upper16:{{.*}}
63 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
64 ; CHECK: movt [[reg0]], :upper16:{{.*}}
94 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
95 ; CHECK: movt [[reg0]], :upper16:{{.*}}
125 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
126 ; CHECK: movt [[reg0]], :upper16:{{.*}}
156 ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}}
157 ; CHECK: movt [[reg0]], :upper16:{{.*}}
[all …]
/external/libyuv/files/source/
Drow_msa.cc481 v16u8 reg0, reg1, reg2, reg3; in I422ToRGB24Row_MSA() local
506 reg0 = (v16u8)__msa_ilvev_b((v16i8)vec1, (v16i8)vec0); in I422ToRGB24Row_MSA()
509 reg1 = (v16u8)__msa_sldi_b((v16i8)reg2, (v16i8)reg0, 11); in I422ToRGB24Row_MSA()
510 dst0 = (v16u8)__msa_vshf_b(shuffler0, (v16i8)reg3, (v16i8)reg0); in I422ToRGB24Row_MSA()
570 v8u16 reg0, reg1, reg2; in I422ToARGB4444Row_MSA() local
585 reg0 = (v8u16)__msa_srai_h(vec0, 4); in I422ToARGB4444Row_MSA()
591 reg0 |= reg2; in I422ToARGB4444Row_MSA()
592 dst0 = (v16u8)(reg1 | reg0); in I422ToARGB4444Row_MSA()
610 v8u16 reg0, reg1, reg2; in I422ToARGB1555Row_MSA() local
625 reg0 = (v8u16)__msa_srai_h(vec0, 3); in I422ToARGB1555Row_MSA()
[all …]
/external/libvpx/libvpx/third_party/libyuv/source/
Dcompare_msa.cc59 v4i32 reg0 = {0}, reg1 = {0}, reg2 = {0}, reg3 = {0}; in SumSquareError_MSA() local
75 reg0 = __msa_dpadd_s_w(reg0, vec0, vec0); in SumSquareError_MSA()
83 reg0 += reg1; in SumSquareError_MSA()
85 reg0 += reg2; in SumSquareError_MSA()
86 tmp0 = __msa_hadd_s_d(reg0, reg0); in SumSquareError_MSA()
Drow_msa.cc481 v16u8 reg0, reg1, reg2, reg3; in I422ToRGB24Row_MSA() local
506 reg0 = (v16u8)__msa_ilvev_b((v16i8)vec1, (v16i8)vec0); in I422ToRGB24Row_MSA()
509 reg1 = (v16u8)__msa_sldi_b((v16i8)reg2, (v16i8)reg0, 11); in I422ToRGB24Row_MSA()
510 dst0 = (v16u8)__msa_vshf_b(shuffler0, (v16i8)reg3, (v16i8)reg0); in I422ToRGB24Row_MSA()
570 v8u16 reg0, reg1, reg2; in I422ToARGB4444Row_MSA() local
585 reg0 = (v8u16)__msa_srai_h(vec0, 4); in I422ToARGB4444Row_MSA()
591 reg0 |= reg2; in I422ToARGB4444Row_MSA()
592 dst0 = (v16u8)(reg1 | reg0); in I422ToARGB4444Row_MSA()
610 v8u16 reg0, reg1, reg2; in I422ToARGB1555Row_MSA() local
625 reg0 = (v8u16)__msa_srai_h(vec0, 3); in I422ToARGB1555Row_MSA()
[all …]
Dscale_msa.cc78 v8u16 reg0, reg1, reg2, reg3; in ScaleARGBRowDown2Box_MSA() local
90 reg0 = __msa_hadd_u_h(vec0, vec0); in ScaleARGBRowDown2Box_MSA()
94 reg0 += reg2; in ScaleARGBRowDown2Box_MSA()
96 reg0 = (v8u16)__msa_srari_h((v8i16)reg0, 2); in ScaleARGBRowDown2Box_MSA()
98 dst0 = (v16u8)__msa_pckev_b((v16i8)reg1, (v16i8)reg0); in ScaleARGBRowDown2Box_MSA()
141 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
165 reg0 = __msa_hadd_u_h(vec0, vec0); in ScaleARGBRowDownEvenBox_MSA()
169 reg4 = (v8u16)__msa_pckev_d((v2i64)reg2, (v2i64)reg0); in ScaleARGBRowDownEvenBox_MSA()
171 reg6 = (v8u16)__msa_pckod_d((v2i64)reg2, (v2i64)reg0); in ScaleARGBRowDownEvenBox_MSA()
304 v4u32 reg0, reg1, reg2, reg3; in ScaleRowDown4Box_MSA() local
[all …]
/external/u-boot/scripts/coccinelle/net/
Dmdio_register.cocci28 identifier name0, addr0, reg0, output;
35 - addrT reg0,
42 + int reg0
111 identifier name0, addr0, reg0, value0;
119 - addrT reg0,
126 + int reg0,
/external/libhevc/encoder/arm/
Dihevce_common_utils_neon.c112 int32x4_t reg0[4], reg1[4]; in ihevce_wt_avg_2d_16x1_neon() local
129 reg0[0] = vmovl_s16(vget_low_s16(a2)); in ihevce_wt_avg_2d_16x1_neon()
130 reg0[1] = vmovl_s16(vget_high_s16(a2)); in ihevce_wt_avg_2d_16x1_neon()
131 reg0[2] = vmovl_s16(vget_low_s16(a3)); in ihevce_wt_avg_2d_16x1_neon()
132 reg0[3] = vmovl_s16(vget_high_s16(a3)); in ihevce_wt_avg_2d_16x1_neon()
139 reg0[0] = vmulq_s32(reg0[0], a6); in ihevce_wt_avg_2d_16x1_neon()
140 reg0[1] = vmulq_s32(reg0[1], a6); in ihevce_wt_avg_2d_16x1_neon()
141 reg0[2] = vmulq_s32(reg0[2], a6); in ihevce_wt_avg_2d_16x1_neon()
142 reg0[3] = vmulq_s32(reg0[3], a6); in ihevce_wt_avg_2d_16x1_neon()
149 reg0[0] = vaddq_s32(reg0[0], reg1[0]); in ihevce_wt_avg_2d_16x1_neon()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dtex-clause-antidep.ll6 define amdgpu_vs void @test(<4 x float> inreg %reg0) {
7 %1 = extractelement <4 x float> %reg0, i32 0
8 %2 = extractelement <4 x float> %reg0, i32 1
9 %3 = extractelement <4 x float> %reg0, i32 2
10 %4 = extractelement <4 x float> %reg0, i32 3
/external/llvm/test/CodeGen/AMDGPU/
Dtex-clause-antidep.ll6 define amdgpu_vs void @test(<4 x float> inreg %reg0) {
7 %1 = extractelement <4 x float> %reg0, i32 0
8 %2 = extractelement <4 x float> %reg0, i32 1
9 %3 = extractelement <4 x float> %reg0, i32 2
10 %4 = extractelement <4 x float> %reg0, i32 3

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