| /external/libvpx/libvpx/vpx_ports/ |
| D | asmdefs_mmi.h | 21 #define MMI_ADDU(reg1, reg2, reg3) \ argument
22 "daddu " #reg1 ", " #reg2 ", " #reg3 " \n\t"
24 #define MMI_ADDIU(reg1, reg2, immediate) \ argument
25 "daddiu " #reg1 ", " #reg2 ", " #immediate " \n\t"
27 #define MMI_ADDI(reg1, reg2, immediate) \ argument
28 "daddi " #reg1 ", " #reg2 ", " #immediate " \n\t"
30 #define MMI_SUBU(reg1, reg2, reg3) \ argument
31 "dsubu " #reg1 ", " #reg2 ", " #reg3 " \n\t"
36 #define MMI_SRL(reg1, reg2, shift) \ argument
37 "dsrl " #reg1 ", " #reg2 ", " #shift " \n\t"
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| /external/libvpx/libvpx/vpx_dsp/mips/ |
| D | idct32x32_msa.c | 44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
50 DOTP_CONST_PAIR(reg1, reg7, cospi_28_64, cospi_4_64, reg1, reg7); in idct32x8_row_even_process_store()
52 BUTTERFLY_4(reg1, reg7, reg3, reg5, vec1, vec3, vec2, vec0); in idct32x8_row_even_process_store()
65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
69 DOTP_CONST_PAIR(reg6, reg1, cospi_6_64, cospi_26_64, reg6, reg1); in idct32x8_row_even_process_store()
75 reg2 = reg1 + reg5; in idct32x8_row_even_process_store()
76 reg1 = reg1 - reg5; in idct32x8_row_even_process_store()
88 DOTP_CONST_PAIR((-reg6), reg1, cospi_24_64, cospi_8_64, reg6, reg1); in idct32x8_row_even_process_store()
92 vec1 = reg7 - reg1; in idct32x8_row_even_process_store()
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| D | idct16x16_msa.c | 16 v8i16 reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15; in vpx_idct16_1d_rows_msa() local
19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg0, reg1, in vpx_idct16_1d_rows_msa()
40 DOTP_CONST_PAIR(reg1, reg15, cospi_30_64, cospi_2_64, reg1, reg15); in vpx_idct16_1d_rows_msa()
43 reg9 = reg1 - loc2; in vpx_idct16_1d_rows_msa()
44 reg1 = reg1 + loc2; in vpx_idct16_1d_rows_msa()
57 loc1 = reg1 + reg13; in vpx_idct16_1d_rows_msa()
58 reg13 = reg1 - reg13; in vpx_idct16_1d_rows_msa()
71 reg1 = reg6 - loc0; in vpx_idct16_1d_rows_msa()
101 TRANSPOSE8x8_SH_SH(reg3, reg13, reg11, reg5, reg7, reg9, reg1, reg15, reg3, in vpx_idct16_1d_rows_msa()
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| /external/u-boot/post/lib_powerpc/ |
| D | rlwimi.c | 63 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_rlwimi() local
72 ASM_STW(reg1, stk, 0), in cpu_post_test_rlwimi()
73 ASM_LWZ(reg1, stk, 8), in cpu_post_test_rlwimi()
75 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me), in cpu_post_test_rlwimi()
76 ASM_STW(reg1, stk, 8), in cpu_post_test_rlwimi()
77 ASM_LWZ(reg1, stk, 0), in cpu_post_test_rlwimi()
91 ASM_STW(reg1, stk, 0), in cpu_post_test_rlwimi()
92 ASM_LWZ(reg1, stk, 8), in cpu_post_test_rlwimi()
94 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me) | in cpu_post_test_rlwimi()
96 ASM_STW(reg1, stk, 8), in cpu_post_test_rlwimi()
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| D | two.c | 82 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_two() local
90 ASM_STW(reg1, stk, 0), in cpu_post_test_two()
92 ASM_11(test->cmd, reg1, reg0), in cpu_post_test_two()
93 ASM_STW(reg1, stk, 8), in cpu_post_test_two()
94 ASM_LWZ(reg1, stk, 0), in cpu_post_test_two()
107 ASM_STW(reg1, stk, 0), in cpu_post_test_two()
109 ASM_11(test->cmd, reg1, reg0) | BIT_C, in cpu_post_test_two()
110 ASM_STW(reg1, stk, 8), in cpu_post_test_two()
111 ASM_LWZ(reg1, stk, 0), in cpu_post_test_two()
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| D | twox.c | 82 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_twox() local
90 ASM_STW(reg1, stk, 0), in cpu_post_test_twox()
92 ASM_11X(test->cmd, reg1, reg0), in cpu_post_test_twox()
93 ASM_STW(reg1, stk, 8), in cpu_post_test_twox()
94 ASM_LWZ(reg1, stk, 0), in cpu_post_test_twox()
107 ASM_STW(reg1, stk, 0), in cpu_post_test_twox()
109 ASM_11X(test->cmd, reg1, reg0) | BIT_C, in cpu_post_test_twox()
110 ASM_STW(reg1, stk, 8), in cpu_post_test_twox()
111 ASM_LWZ(reg1, stk, 0), in cpu_post_test_twox()
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| D | srawi.c | 62 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_srawi() local
70 ASM_STW(reg1, stk, 0), in cpu_post_test_srawi()
72 ASM_11S(test->cmd, reg1, reg0, test->op2), in cpu_post_test_srawi()
73 ASM_STW(reg1, stk, 8), in cpu_post_test_srawi()
74 ASM_LWZ(reg1, stk, 0), in cpu_post_test_srawi()
87 ASM_STW(reg1, stk, 0), in cpu_post_test_srawi()
89 ASM_11S(test->cmd, reg1, reg0, test->op2) | BIT_C, in cpu_post_test_srawi()
90 ASM_STW(reg1, stk, 8), in cpu_post_test_srawi()
91 ASM_LWZ(reg1, stk, 0), in cpu_post_test_srawi()
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| D | rlwinm.c | 60 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_rlwinm() local
68 ASM_STW(reg1, stk, 0), in cpu_post_test_rlwinm()
70 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me), in cpu_post_test_rlwinm()
71 ASM_STW(reg1, stk, 8), in cpu_post_test_rlwinm()
72 ASM_LWZ(reg1, stk, 0), in cpu_post_test_rlwinm()
85 ASM_STW(reg1, stk, 0), in cpu_post_test_rlwinm()
87 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, in cpu_post_test_rlwinm()
89 ASM_STW(reg1, stk, 8), in cpu_post_test_rlwinm()
90 ASM_LWZ(reg1, stk, 0), in cpu_post_test_rlwinm()
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| D | rlwnm.c | 61 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_rlwnm() local
71 ASM_STW(reg1, stk, 4), in cpu_post_test_rlwnm()
73 ASM_LWZ(reg1, stk, 12), in cpu_post_test_rlwnm()
75 ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me), in cpu_post_test_rlwnm()
78 ASM_LWZ(reg1, stk, 4), in cpu_post_test_rlwnm()
92 ASM_STW(reg1, stk, 4), in cpu_post_test_rlwnm()
94 ASM_LWZ(reg1, stk, 12), in cpu_post_test_rlwnm()
96 ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me) | in cpu_post_test_rlwnm()
100 ASM_LWZ(reg1, stk, 4), in cpu_post_test_rlwnm()
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| D | threex.c | 126 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_threex() local
136 ASM_STW(reg1, stk, 4), in cpu_post_test_threex()
138 ASM_LWZ(reg1, stk, 12), in cpu_post_test_threex()
140 ASM_12X(test->cmd, reg2, reg1, reg0), in cpu_post_test_threex()
143 ASM_LWZ(reg1, stk, 4), in cpu_post_test_threex()
157 ASM_STW(reg1, stk, 4), in cpu_post_test_threex()
159 ASM_LWZ(reg1, stk, 12), in cpu_post_test_threex()
161 ASM_12X(test->cmd, reg2, reg1, reg0) | BIT_C, in cpu_post_test_threex()
164 ASM_LWZ(reg1, stk, 4), in cpu_post_test_threex()
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| D | three.c | 156 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_three() local
166 ASM_STW(reg1, stk, 4), in cpu_post_test_three()
168 ASM_LWZ(reg1, stk, 12), in cpu_post_test_three()
170 ASM_12(test->cmd, reg2, reg1, reg0), in cpu_post_test_three()
173 ASM_LWZ(reg1, stk, 4), in cpu_post_test_three()
187 ASM_STW(reg1, stk, 4), in cpu_post_test_three()
189 ASM_LWZ(reg1, stk, 12), in cpu_post_test_three()
191 ASM_12(test->cmd, reg2, reg1, reg0) | BIT_C, in cpu_post_test_three()
194 ASM_LWZ(reg1, stk, 4), in cpu_post_test_three()
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| D | andi.c | 62 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_andi() local
70 ASM_STW(reg1, stk, 0), in cpu_post_test_andi()
72 ASM_11IX(test->cmd, reg1, reg0, test->op2), in cpu_post_test_andi()
73 ASM_STW(reg1, stk, 8), in cpu_post_test_andi()
74 ASM_LWZ(reg1, stk, 0), in cpu_post_test_andi()
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| D | threei.c | 76 unsigned int reg1 = (reg + 1) % 32; in cpu_post_test_threei() local
84 ASM_STW(reg1, stk, 0), in cpu_post_test_threei()
86 ASM_11IX(test->cmd, reg1, reg0, test->op2), in cpu_post_test_threei()
87 ASM_STW(reg1, stk, 8), in cpu_post_test_threei()
88 ASM_LWZ(reg1, stk, 0), in cpu_post_test_threei()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | max-literals.ll | 6 define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %re…
8 %0 = extractelement <4 x float> %reg1, i32 0
9 %1 = extractelement <4 x float> %reg1, i32 1
10 %2 = extractelement <4 x float> %reg1, i32 2
11 %3 = extractelement <4 x float> %reg1, i32 3
35 define amdgpu_vs void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %r…
37 %0 = extractelement <4 x float> %reg1, i32 0
38 %1 = extractelement <4 x float> %reg1, i32 1
39 %2 = extractelement <4 x float> %reg1, i32 2
40 %3 = extractelement <4 x float> %reg1, i32 3
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | max-literals.ll | 6 define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %re…
8 %0 = extractelement <4 x float> %reg1, i32 0
9 %1 = extractelement <4 x float> %reg1, i32 1
10 %2 = extractelement <4 x float> %reg1, i32 2
11 %3 = extractelement <4 x float> %reg1, i32 3
35 define amdgpu_vs void @main2(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %r…
37 %0 = extractelement <4 x float> %reg1, i32 0
38 %1 = extractelement <4 x float> %reg1, i32 1
39 %2 = extractelement <4 x float> %reg1, i32 2
40 %3 = extractelement <4 x float> %reg1, i32 3
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| /external/libmpeg2/common/armv8/ |
| D | impeg2_neon_macros.s | 53 .macro swp reg1, reg2
54 eor \reg1, \reg1, \reg2
55 eor \reg2, \reg1, \reg2
56 eor \reg1, \reg1, \reg2
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| /external/libavc/common/armv8/ |
| D | ih264_neon_macros.s | 36 .macro swp reg1, reg2
37 eor \reg1, \reg1, \reg2
38 eor \reg2, \reg1, \reg2
39 eor \reg1, \reg1, \reg2
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| /external/libyuv/files/source/ |
| D | row_msa.cc | 481 v16u8 reg0, reg1, reg2, reg3; in I422ToRGB24Row_MSA() local
509 reg1 = (v16u8)__msa_sldi_b((v16i8)reg2, (v16i8)reg0, 11); in I422ToRGB24Row_MSA()
511 dst1 = (v16u8)__msa_vshf_b(shuffler1, (v16i8)reg3, (v16i8)reg1); in I422ToRGB24Row_MSA()
570 v8u16 reg0, reg1, reg2; in I422ToARGB4444Row_MSA() local
586 reg1 = (v8u16)__msa_srai_h(vec1, 4); in I422ToARGB4444Row_MSA()
588 reg1 = (v8u16)__msa_slli_h((v8i16)reg1, 4); in I422ToARGB4444Row_MSA()
590 reg1 |= const_0xF000; in I422ToARGB4444Row_MSA()
592 dst0 = (v16u8)(reg1 | reg0); in I422ToARGB4444Row_MSA()
610 v8u16 reg0, reg1, reg2; in I422ToARGB1555Row_MSA() local
626 reg1 = (v8u16)__msa_srai_h(vec1, 3); in I422ToARGB1555Row_MSA()
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| /external/boringssl/src/crypto/perlasm/ |
| D | x86gas.pl | 77 { my($addr,$reg1,$reg2,$idx)=@_;
80 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
86 $reg1 = "%$reg1" if ($reg1);
93 $ret .= "($reg1,$reg2,$idx)";
95 elsif ($reg1)
96 { $ret .= "($reg1)"; }
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| D | x86masm.pl | 46 { my($size,$addr,$reg1,$reg2,$idx)=@_;
49 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
68 $ret .= "+$reg1" if ($reg1 ne "");
71 { $ret .= "$reg1"; }
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| D | x86nasm.pl | 43 { my($size,$addr,$reg1,$reg2,$idx)=@_;
46 if (!defined($idx) && 1*$reg2) { $idx=$reg2; $reg2=$reg1; undef $reg1; }
69 $ret .= "+$reg1" if ($reg1 ne "");
72 { $ret .= "$reg1"; }
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| /external/libvpx/libvpx/third_party/libyuv/source/ |
| D | scale_msa.cc | 78 v8u16 reg0, reg1, reg2, reg3; in ScaleARGBRowDown2Box_MSA() local
91 reg1 = __msa_hadd_u_h(vec1, vec1); in ScaleARGBRowDown2Box_MSA()
95 reg1 += reg3; in ScaleARGBRowDown2Box_MSA()
97 reg1 = (v8u16)__msa_srari_h((v8i16)reg1, 2); in ScaleARGBRowDown2Box_MSA()
98 dst0 = (v16u8)__msa_pckev_b((v16i8)reg1, (v16i8)reg0); in ScaleARGBRowDown2Box_MSA()
141 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
166 reg1 = __msa_hadd_u_h(vec1, vec1); in ScaleARGBRowDownEvenBox_MSA()
170 reg5 = (v8u16)__msa_pckev_d((v2i64)reg3, (v2i64)reg1); in ScaleARGBRowDownEvenBox_MSA()
172 reg7 = (v8u16)__msa_pckod_d((v2i64)reg3, (v2i64)reg1); in ScaleARGBRowDownEvenBox_MSA()
304 v4u32 reg0, reg1, reg2, reg3; in ScaleRowDown4Box_MSA() local
[all …]
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| D | row_msa.cc | 481 v16u8 reg0, reg1, reg2, reg3; in I422ToRGB24Row_MSA() local
509 reg1 = (v16u8)__msa_sldi_b((v16i8)reg2, (v16i8)reg0, 11); in I422ToRGB24Row_MSA()
511 dst1 = (v16u8)__msa_vshf_b(shuffler1, (v16i8)reg3, (v16i8)reg1); in I422ToRGB24Row_MSA()
570 v8u16 reg0, reg1, reg2; in I422ToARGB4444Row_MSA() local
586 reg1 = (v8u16)__msa_srai_h(vec1, 4); in I422ToARGB4444Row_MSA()
588 reg1 = (v8u16)__msa_slli_h((v8i16)reg1, 4); in I422ToARGB4444Row_MSA()
590 reg1 |= const_0xF000; in I422ToARGB4444Row_MSA()
592 dst0 = (v16u8)(reg1 | reg0); in I422ToARGB4444Row_MSA()
610 v8u16 reg0, reg1, reg2; in I422ToARGB1555Row_MSA() local
626 reg1 = (v8u16)__msa_srai_h(vec1, 3); in I422ToARGB1555Row_MSA()
[all …]
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| /external/elfutils/tests/ |
| D | run-dwarfcfi.sh | 39 reg1: undefined
56 reg1: undefined
73 reg1: location expression: call_frame_cfa stack_value
90 reg1: location expression: call_frame_cfa stack_value
107 reg1: undefined
124 reg1: undefined
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| /external/u-boot/arch/arm/lib/ |
| D | memcpy.S | 20 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
21 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
24 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
25 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
36 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
37 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
44 .macro enter reg1 reg2
45 stmdb sp!, {r0, \reg1, \reg2}
48 .macro exit reg1 reg2
49 ldmfd sp!, {r0, \reg1, \reg2}
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