| /external/libvpx/libvpx/vpx_dsp/mips/ |
| D | idct32x32_msa.c | 44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in idct32x8_row_even_process_store() local
48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
58 DOTP_CONST_PAIR(reg0, reg4, cospi_16_64, cospi_16_64, reg0, reg4); in idct32x8_row_even_process_store()
60 BUTTERFLY_4(reg4, reg0, reg2, reg6, vec1, vec3, vec2, vec0); in idct32x8_row_even_process_store()
65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in idct32x8_row_even_process_store()
67 DOTP_CONST_PAIR(reg4, reg3, cospi_14_64, cospi_18_64, reg4, reg3); in idct32x8_row_even_process_store()
71 vec0 = reg0 + reg4; in idct32x8_row_even_process_store()
72 reg0 = reg0 - reg4; in idct32x8_row_even_process_store()
73 reg4 = reg6 + reg2; in idct32x8_row_even_process_store()
82 reg2 = reg3 + reg4; in idct32x8_row_even_process_store()
[all …]
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| D | idct16x16_msa.c | 15 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vpx_idct16_1d_rows_msa() local
19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg0, reg1, in vpx_idct16_1d_rows_msa()
24 reg2, reg3, reg4, reg5, reg6, reg7); in vpx_idct16_1d_rows_msa()
32 DOTP_CONST_PAIR(reg4, reg12, cospi_24_64, cospi_8_64, reg4, reg12); in vpx_idct16_1d_rows_msa()
33 BUTTERFLY_4(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14); in vpx_idct16_1d_rows_msa()
34 SUB4(reg2, loc1, reg14, loc0, reg6, loc3, reg10, loc2, reg0, reg12, reg4, in vpx_idct16_1d_rows_msa()
75 loc1 = reg4 + loc0; in vpx_idct16_1d_rows_msa()
76 loc2 = reg4 - loc0; in vpx_idct16_1d_rows_msa()
80 BUTTERFLY_4(reg8, reg10, reg11, reg5, loc0, reg4, reg9, loc1); in vpx_idct16_1d_rows_msa()
[all …]
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| /external/elfutils/tests/ |
| D | run-varlocs.sh | 59 [400500,400504) {reg4}
67 [400510,40051c) {reg4}
69 [40052a,400531) {GNU_entry_value(1) {reg4}, stack_value}
82 [400400,400403) {reg4}
83 [400403,40040b) {GNU_entry_value(1) {reg4}, stack_value}
110 [400400,400408) {reg4}
111 [400408,400423) {GNU_entry_value(1) {reg4}, stack_value}
147 [401050,401066) {reg4}
148 [401066,401067) {entry_value(1) {reg4}, stack_value}
159 [401150,401160) {reg4}
[all …]
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| D | run-dwarfcfi.sh | 42 reg4: location expression: call_frame_cfa stack_value
59 reg4: undefined
76 reg4: undefined
93 reg4: undefined
110 reg4: same_value
127 reg4: undefined
|
| D | run-readelf-loc.sh | 297 [ 0] reg4
302 [ 0] reg4
453 [ 0] reg4
458 [ 0] reg4
659 [ 0] reg4
664 [ 0] reg4
817 [ 0] reg4
822 [ 0] reg4
1114 [ 0] reg4
1119 [ 0] reg4
[all …]
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| /external/libyuv/files/source/ |
| D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
109 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeWx16_MSA()
110 ILVRL_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3); in TransposeWx16_MSA()
131 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeWx16_MSA()
132 res8 = (v16u8)__msa_ilvr_w((v4i32)reg4, (v4i32)reg0); in TransposeWx16_MSA()
133 res9 = (v16u8)__msa_ilvl_w((v4i32)reg4, (v4i32)reg0); in TransposeWx16_MSA()
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
190 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeUVWx16_MSA()
191 ILVRL_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3); in TransposeUVWx16_MSA()
212 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeUVWx16_MSA()
[all …]
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| D | row_msa.cc | 774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGBToYRow_MSA() local
794 reg4 = (v8u16)__msa_ilvod_b(zero, (v16i8)vec0); in ARGBToYRow_MSA()
800 reg4 *= const_0x42; in ARGBToYRow_MSA()
804 reg0 += reg4; in ARGBToYRow_MSA()
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
862 reg4 = __msa_hadd_u_h(vec0, vec0); in ARGBToUVRow_MSA()
890 reg4 += __msa_hadd_u_h(vec0, vec0); in ARGBToUVRow_MSA()
896 reg4 = (v8u16)__msa_srai_h((v8i16)reg4, 2); in ARGBToUVRow_MSA()
904 reg8 += reg4 * const_0x26; in ARGBToUVRow_MSA()
910 reg4 *= const_0x70; in ARGBToUVRow_MSA()
[all …]
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| D | scale_msa.cc | 133 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
161 reg4 = (v8u16)__msa_pckev_d((v2i64)reg2, (v2i64)reg0); in ScaleARGBRowDownEvenBox_MSA()
165 reg4 += reg6; in ScaleARGBRowDownEvenBox_MSA()
167 reg4 = (v8u16)__msa_srari_h((v8i16)reg4, 2); in ScaleARGBRowDownEvenBox_MSA()
169 dst0 = (v16u8)__msa_pckev_b((v16i8)reg5, (v16i8)reg4); in ScaleARGBRowDownEvenBox_MSA()
|
| /external/libvpx/libvpx/third_party/libyuv/source/ |
| D | rotate_msa.cc | 85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeWx16_MSA() local
109 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeWx16_MSA()
110 ILVRL_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3); in TransposeWx16_MSA()
131 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeWx16_MSA()
132 res8 = (v16u8)__msa_ilvr_w((v4i32)reg4, (v4i32)reg0); in TransposeWx16_MSA()
133 res9 = (v16u8)__msa_ilvl_w((v4i32)reg4, (v4i32)reg0); in TransposeWx16_MSA()
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in TransposeUVWx16_MSA() local
190 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeUVWx16_MSA()
191 ILVRL_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3); in TransposeUVWx16_MSA()
212 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7); in TransposeUVWx16_MSA()
[all …]
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| D | scale_msa.cc | 141 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBRowDownEvenBox_MSA() local
169 reg4 = (v8u16)__msa_pckev_d((v2i64)reg2, (v2i64)reg0); in ScaleARGBRowDownEvenBox_MSA()
173 reg4 += reg6; in ScaleARGBRowDownEvenBox_MSA()
175 reg4 = (v8u16)__msa_srari_h((v8i16)reg4, 2); in ScaleARGBRowDownEvenBox_MSA()
177 dst0 = (v16u8)__msa_pckev_b((v16i8)reg5, (v16i8)reg4); in ScaleARGBRowDownEvenBox_MSA()
669 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; in ScaleARGBFilterCols_MSA() local
705 reg4 = (v16u8)__msa_ilvr_b((v16i8)src2, (v16i8)src0); in ScaleARGBFilterCols_MSA()
709 tmp0 = __msa_dotp_u_h(reg4, mult0); in ScaleARGBFilterCols_MSA()
766 v8i16 reg0, reg1, reg2, reg3, reg4, reg5; in ScaleRowDown34_0_Box_MSA() local
806 reg4 = (v8i16)__msa_dotp_u_h(vec4, const1); in ScaleRowDown34_0_Box_MSA()
[all …]
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| D | row_msa.cc | 774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; in ARGBToYRow_MSA() local
794 reg4 = (v8u16)__msa_ilvod_b(zero, (v16i8)vec0); in ARGBToYRow_MSA()
800 reg4 *= const_0x42; in ARGBToYRow_MSA()
804 reg0 += reg4; in ARGBToYRow_MSA()
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; in ARGBToUVRow_MSA() local
862 reg4 = __msa_hadd_u_h(vec0, vec0); in ARGBToUVRow_MSA()
890 reg4 += __msa_hadd_u_h(vec0, vec0); in ARGBToUVRow_MSA()
896 reg4 = (v8u16)__msa_srai_h((v8i16)reg4, 2); in ARGBToUVRow_MSA()
904 reg8 += reg4 * const_0x26; in ARGBToUVRow_MSA()
910 reg4 *= const_0x70; in ARGBToUVRow_MSA()
[all …]
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| /external/v8/src/interpreter/ |
| D | bytecode-register.cc | 98 Register reg4, Register reg5) { in AreContiguous() argument
105 if (reg4.is_valid() && reg3.index() + 1 != reg4.index()) { in AreContiguous()
108 if (reg5.is_valid() && reg4.index() + 1 != reg5.index()) { in AreContiguous()
|
| /external/llvm/test/CodeGen/ARM/ |
| D | fast-isel-pic.ll | 45 ; THUMB-ELF: ldr r[[reg4:[0-9]+]], [r[[reg3]]]
46 ; THUMB-ELF: ldr r0, [r[[reg4]]]
48 ; ARM: ldr [[reg4:r[0-9]+]],
49 ; ARM: ldr [[reg4]], [pc, [[reg4]]]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | fast-isel-pic.ll | 45 ; THUMB-ELF: ldr r[[reg4:[0-9]+]], [r[[reg3]]]
46 ; THUMB-ELF: ldr r0, [r[[reg4]]]
48 ; ARM: ldr [[reg4:r[0-9]+]],
49 ; ARM: ldr [[reg4]], [pc, [[reg4]]]
|
| /external/u-boot/board/freescale/ls1046ardb/ |
| D | cpld.c | 31 u8 reg4 = CPLD_READ(soft_mux_on); in cpld_set_altbank() local
38 CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); in cpld_set_altbank()
53 u8 reg4 = CPLD_READ(soft_mux_on); in cpld_set_defbank() local
59 CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); in cpld_set_defbank()
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| /external/u-boot/board/freescale/ls1043ardb/ |
| D | cpld.c | 31 u8 reg4 = CPLD_READ(soft_mux_on); in cpld_set_altbank() local
38 CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); in cpld_set_altbank()
53 u8 reg4 = CPLD_READ(soft_mux_on); in cpld_set_defbank() local
59 CPLD_WRITE(soft_mux_on, reg4 | CPLD_SW_MUX_BANK_SEL | 1); in cpld_set_defbank()
|
| /external/u-boot/arch/arm/lib/ |
| D | memcpy.S | 20 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
21 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
24 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
25 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
36 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
37 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
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| /external/vixl/src/aarch64/ |
| D | operands-aarch64.h | 487 const CPURegister& reg4 = NoReg,
501 const CPURegister& reg4 = NoCPUReg,
513 const CPURegister& reg4 = NoReg,
527 const CPURegister& reg4 = NoCPUReg);
536 const VRegister& reg4 = NoVReg);
546 const VRegister& reg4 = NoVReg);
555 CPURegister reg4 = NoCPUReg)
556 : list_(reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit()),
559 VIXL_ASSERT(AreSameSizeAndType(reg1, reg2, reg3, reg4));
|
| /external/u-boot/arch/arm/cpu/arm1136/mx35/ |
| D | generic.c | 196 u32 reg4 = readl(&ccm->pdr4); in mxc_get_main_clock() local
229 nfc_pdf = (reg4 >> 28) & 0xF; in mxc_get_main_clock()
235 usb_podf = (reg4 >> 22) & 0x3F; in mxc_get_main_clock()
236 if (reg4 & 0x200) in mxc_get_main_clock()
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| /external/u-boot/board/gdsys/common/ |
| D | osd.c | 203 u8 reg0, reg4, reg8, reg12, reg18, reg20; in ics8n3qv01_set() local
218 reg4 = mfrac >> 9; in ics8n3qv01_set()
219 i2c_reg_write(ICS8N3QV01_I2C_ADDR, 4, reg4); in ics8n3qv01_set()
|
| /external/libxml2/result/HTML/ |
| D | reg4.html.err | 1 ./test/HTML/reg4.html:10: HTML parser error : Unexpected end tag : p
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | pv.ll | 6 …eg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg %reg4, <4 x float> inreg …
20 %12 = extractelement <4 x float> %reg4, i32 0
21 %13 = extractelement <4 x float> %reg4, i32 1
22 %14 = extractelement <4 x float> %reg4, i32 2
23 %15 = extractelement <4 x float> %reg4, i32 3
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/DebugInfo/ |
| D | dwarfdump-debug-frame-simple.test | 8 ; FRAMES: DW_CFA_def_cfa: reg4 +4
|
| /external/llvm/test/DebugInfo/ |
| D | dwarfdump-debug-frame-simple.test | 9 ; FRAMES: DW_CFA_def_cfa: reg4 +4
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | pv.ll | 5 …eg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 x float> inreg %reg4, <4 x float> inreg …
19 %tmp24 = extractelement <4 x float> %reg4, i32 0
20 %tmp25 = extractelement <4 x float> %reg4, i32 1
21 %tmp26 = extractelement <4 x float> %reg4, i32 2
22 %tmp27 = extractelement <4 x float> %reg4, i32 3
|