Searched refs:regValue (Results 1 – 7 of 7) sorted by relevance
164 ADDR_REGISTER_VALUE regValue = {0}; in amdgpu_addr_create() local172 regValue.gbAddrConfig = amdinfo->gb_addr_cfg; in amdgpu_addr_create()181 regValue.blockVarSizeLog2 = 0; in amdgpu_addr_create()183 regValue.noOfBanks = amdinfo->mc_arb_ramcfg & 0x3; in amdgpu_addr_create()184 regValue.noOfRanks = (amdinfo->mc_arb_ramcfg & 0x4) >> 2; in amdgpu_addr_create()186 regValue.backendDisables = amdinfo->enabled_rb_pipes_mask; in amdgpu_addr_create()187 regValue.pTileConfig = amdinfo->gb_tile_mode; in amdgpu_addr_create()188 regValue.noOfEntries = ARRAY_SIZE(amdinfo->gb_tile_mode); in amdgpu_addr_create()190 regValue.pMacroTileConfig = NULL; in amdgpu_addr_create()191 regValue.noOfMacroEntries = 0; in amdgpu_addr_create()[all …]
153 UINT_32 regValue, TileConfig* pCfg) const;156 UINT_32 regValue, ADDR_TILEINFO* pCfg) const;
436 const ADDR_REGISTER_VALUE* pRegValue = &pCreateIn->regValue; in HwlInitGlobalParams()1579 UINT_32 regValue, ///< [in] GB_TILE_MODE register in ReadGbTileMode() argument1584 gbTileMode.val = regValue; in ReadGbTileMode()1722 UINT_32 regValue, ///< [in] GB_MACRO_TILE_MODE register in ReadGbMacroTileCfg() argument1727 gbTileMode.val = regValue; in ReadGbMacroTileCfg()
337 VOID ReadGbTileMode(UINT_32 regValue, TileConfig* pCfg) const;
2335 const ADDR_REGISTER_VALUE* pRegValue = &pCreateIn->regValue; in HwlInitGlobalParams()3041 UINT_32 regValue, ///< [in] GB_TILE_MODE register in ReadGbTileMode() argument3046 gbTileMode.val = regValue; in ReadGbTileMode()
373 ADDR_REGISTER_VALUE regValue; ///< Data from registers to setup AddrLib global data member
1001 gbAddrConfig.u32All = pCreateIn->regValue.gbAddrConfig; in HwlInitGlobalParams()1150 m_blockVarSizeLog2 = pCreateIn->regValue.blockVarSizeLog2; in HwlInitGlobalParams()