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Searched refs:reg_addr (Results 1 – 25 of 40) sorted by relevance

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/external/rmi4utils/f54test/
Df54test.cpp544 unsigned short reg_addr = m_f54.GetControlBase(); in SetupF54Controls() local
549 reg_addr += CONTROL_0_SIZE; in SetupF54Controls()
554 reg_addr += CONTROL_1_SIZE; in SetupF54Controls()
557 reg_addr += CONTROL_2_SIZE; in SetupF54Controls()
561 reg_addr += CONTROL_3_SIZE; in SetupF54Controls()
566 reg_addr += CONTROL_4_6_SIZE; in SetupF54Controls()
570 m_f54Control.reg_7.address = reg_addr; in SetupF54Controls()
571 reg_addr += CONTROL_7_SIZE; in SetupF54Controls()
577 reg_addr += CONTROL_8_9_SIZE; in SetupF54Controls()
581 reg_addr += CONTROL_10_SIZE; in SetupF54Controls()
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/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_training_pbs.c46 u32 reg_addr = 0; in ddr3_tip_pbs() local
69 reg_addr = (pbs_mode == PBS_RX_MODE) ? in ddr3_tip_pbs()
72 ddr3_tip_read_adll_value(dev_num, nominal_adll, reg_addr, MASK_ALL_BITS); in ddr3_tip_pbs()
183 reg_addr = (pbs_mode == PBS_RX_MODE) ? in ddr3_tip_pbs()
189 reg_addr, 0x1f)); in ddr3_tip_pbs()
190 reg_addr = (pbs_mode == PBS_RX_MODE) ? in ddr3_tip_pbs()
196 reg_addr, 0x1f)); in ddr3_tip_pbs()
243 reg_addr = (pbs_mode == PBS_RX_MODE) ? in ddr3_tip_pbs()
251 DDR_PHY_DATA, reg_addr, in ddr3_tip_pbs()
253 reg_addr = (pbs_mode == PBS_RX_MODE) ? in ddr3_tip_pbs()
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Dddr3_training_ip_flow.h109 u32 reg_addr; member
133 u32 if_id, u32 reg_addr, u32 data_value, u32 mask);
138 u32 if_id, u32 reg_addr, u32 *data, u32 mask);
143 u32 reg_addr, u32 data_value, u32 reg_mask);
145 u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr,
149 enum hws_ddr_phy e_phy_type, u32 reg_addr,
155 int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr,
157 int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr,
184 int reg_addr, u32 mask);
187 u32 reg_addr, u32 mask);
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Dddr3_training_hw_algo.c162 u32 reg_addr = 0xa8; in ddr3_tip_vref() local
201 DDR_PHY_DATA, reg_addr, &val)); in ddr3_tip_vref()
205 pup, DDR_PHY_DATA, reg_addr, in ddr3_tip_vref()
375 DDR_PHY_DATA, reg_addr, in ddr3_tip_vref()
383 DDR_PHY_DATA, reg_addr, in ddr3_tip_vref()
490 DDR_PHY_DATA, reg_addr, in ddr3_tip_vref()
498 DDR_PHY_DATA, reg_addr, in ddr3_tip_vref()
533 DDR_PHY_DATA, reg_addr, in ddr3_tip_vref()
541 DDR_PHY_DATA, reg_addr, in ddr3_tip_vref()
563 DDR_PHY_DATA, reg_addr, in ddr3_tip_vref()
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Dddr3_training_ip_prv_if.h42 u32 reg_addr, u32 data, u32 mask);
45 u32 reg_addr, u32 *data, u32 mask);
49 enum hws_ddr_phy phy_type, u32 reg_addr, u32 data);
52 u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr, u32 *data);
102 u32 reg_addr, u32 *data);
105 u32 reg_addr, u32 data,
Dddr3_debug.c111 u32 if_id, reg_addr, data_value, bus_id; in ddr3_tip_reg_dump() local
117 for (reg_addr = 0x1400; reg_addr < 0x19f0; reg_addr += 4) { in ddr3_tip_reg_dump()
118 printf("0x%x ", reg_addr); in ddr3_tip_reg_dump()
123 if_id, reg_addr, read_data, in ddr3_tip_reg_dump()
131 for (reg_addr = 0; reg_addr <= 0xff; reg_addr++) { in ddr3_tip_reg_dump()
132 printf("0x%x ", reg_addr); in ddr3_tip_reg_dump()
142 DDR_PHY_DATA, reg_addr, in ddr3_tip_reg_dump()
153 DDR_PHY_CONTROL, reg_addr, in ddr3_tip_reg_dump()
688 u32 reg_addr, u32 mask) in ddr3_tip_read_adll_value() argument
707 DDR_PHY_DATA, reg_addr, in ddr3_tip_read_adll_value()
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Dddr3_init.h164 int ddr3_tip_reg_write(u32 dev_num, u32 reg_addr, u32 data);
165 int ddr3_tip_reg_read(u32 dev_num, u32 reg_addr, u32 *data, u32 reg_mask);
171 int reg_addr, u32 mask);
173 u32 pup_ph_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], int reg_addr);
Dmv_ddr_plat.c854 int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr, in ddr3_tip_ext_read() argument
860 data[burst_num] = readl(reg_addr + 4 * burst_num); in ddr3_tip_ext_read()
868 int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr, in ddr3_tip_ext_write() argument
873 writel(data[burst_num], reg_addr + 4 * burst_num); in ddr3_tip_ext_write()
1297 while (config_table_ptr[i].reg_addr != 0) { in ddr3_new_tip_dlb_config()
1298 reg_write(config_table_ptr[i].reg_addr, in ddr3_new_tip_dlb_config()
Dddr3_training.c1053 u32 if_id, u32 reg_addr, u32 data_value, u32 mask) in ddr3_tip_if_write() argument
1055 config_func_info[dev_num].mv_ddr_dunit_write(reg_addr, mask, data_value); in ddr3_tip_if_write()
1064 u32 if_id, u32 reg_addr, u32 *data, u32 mask) in ddr3_tip_if_read() argument
1066 config_func_info[dev_num].mv_ddr_dunit_read(reg_addr, mask, data); in ddr3_tip_if_read()
1128 enum hws_ddr_phy phy_type, u32 reg_addr, u32 *data) in ddr3_tip_bus_read() argument
1131 mv_ddr_phy_read(phy_access, phy_id, phy_type, reg_addr, data); in ddr3_tip_bus_read()
1139 u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr, in ddr3_tip_bus_write() argument
1143 mv_ddr_phy_write(phy_access, phy_id, phy_type, reg_addr, data_value, OPERATION_WRITE); in ddr3_tip_bus_write()
1152 enum hws_ddr_phy phy_type, u32 reg_addr, in ddr3_tip_bus_read_modify_write() argument
1170 phy_type, reg_addr, &data_val)); in ddr3_tip_bus_read_modify_write()
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/external/u-boot/arch/arm/mach-mvebu/serdes/a38x/
Dseq_exec.c32 u32 unit_base_reg, unit_offset, data, mask, reg_data, reg_addr; in write_op_execute() local
48 reg_addr = unit_base_reg + unit_offset * serdes_num; in write_op_execute()
51 printf("Write: 0x%x: 0x%x (mask 0x%x) - ", reg_addr, data, mask); in write_op_execute()
54 reg_data = reg_read(reg_addr); in write_op_execute()
60 reg_write(reg_addr, reg_data); in write_op_execute()
87 u32 reg_addr, reg_data; in poll_op_execute() local
105 reg_addr = unit_base_reg + unit_offset * serdes_num; in poll_op_execute()
109 printf("Poll: 0x%x: 0x%x (mask 0x%x)\n", reg_addr, data, mask); in poll_op_execute()
113 reg_data = reg_read(reg_addr) & mask; in poll_op_execute()
/external/u-boot/drivers/video/bridge/
Danx6345.c23 unsigned char reg_addr, unsigned char value) in anx6345_write() argument
31 buf[0] = reg_addr; in anx6345_write()
38 __func__, reg_addr, value, ret); in anx6345_write()
46 unsigned char reg_addr, unsigned char *value) in anx6345_read() argument
54 addr = reg_addr; in anx6345_read()
64 __func__, (int)reg_addr, value, ret); in anx6345_read()
72 static int anx6345_write_r0(struct udevice *dev, unsigned char reg_addr, in anx6345_write_r0() argument
77 return anx6345_write(dev, chip->chip_addr, reg_addr, value); in anx6345_write_r0()
80 static int anx6345_read_r0(struct udevice *dev, unsigned char reg_addr, in anx6345_read_r0() argument
85 return anx6345_read(dev, chip->chip_addr, reg_addr, value); in anx6345_read_r0()
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Dps862x.c36 unsigned char reg_addr, unsigned char value) in ps8622_write() argument
45 buf[0] = reg_addr; in ps8622_write()
52 __func__, reg_addr, value, ret); in ps8622_write()
/external/u-boot/drivers/video/exynos/
Dexynos_dp_lowlevel.h28 unsigned int reg_addr,
31 unsigned int reg_addr,
34 unsigned int reg_addr,
38 unsigned int reg_addr,
43 unsigned int reg_addr);
46 unsigned int reg_addr, unsigned int *data);
49 unsigned int reg_addr, unsigned int count,
Dexynos_dp_lowlevel.c474 unsigned int reg_addr, in exynos_dp_write_byte_to_dpcd() argument
484 reg = AUX_ADDR_7_0(reg_addr); in exynos_dp_write_byte_to_dpcd()
486 reg = AUX_ADDR_15_8(reg_addr); in exynos_dp_write_byte_to_dpcd()
488 reg = AUX_ADDR_19_16(reg_addr); in exynos_dp_write_byte_to_dpcd()
514 unsigned int reg_addr, in exynos_dp_read_byte_from_dpcd() argument
525 reg = AUX_ADDR_7_0(reg_addr); in exynos_dp_read_byte_from_dpcd()
527 reg = AUX_ADDR_15_8(reg_addr); in exynos_dp_read_byte_from_dpcd()
529 reg = AUX_ADDR_19_16(reg_addr); in exynos_dp_read_byte_from_dpcd()
553 unsigned int reg_addr, in exynos_dp_write_bytes_to_dpcd() argument
579 reg = AUX_ADDR_7_0(reg_addr + start_offset); in exynos_dp_write_bytes_to_dpcd()
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/external/u-boot/drivers/net/pfe_eth/
Dpfe_mdio.c17 int reg_addr) in pfe_write_addr() argument
28 reg_data = (EMAC_MII_DATA_TA | phy | devadr | reg_addr); in pfe_write_addr()
51 int reg_addr) in pfe_phy_read() argument
61 reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) << in pfe_phy_read()
64 pfe_write_addr(bus, phy_addr, dev_addr, reg_addr); in pfe_phy_read()
100 phy_addr, reg_addr, val); in pfe_phy_read()
106 int reg_addr, u16 data) in pfe_phy_write() argument
116 reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) << in pfe_phy_write()
119 pfe_write_addr(bus, phy_addr, dev_addr, reg_addr); in pfe_phy_write()
151 reg_addr, data); in pfe_phy_write()
/external/u-boot/cmd/
Dpci.c103 u32 reg_addr; in pci_bar_show() local
119 reg_addr = PCI_BASE_ADDRESS_0; in pci_bar_show()
121 dm_pci_read_config32(dev, reg_addr, &base_low); in pci_bar_show()
122 dm_pci_write_config32(dev, reg_addr, 0xffffffff); in pci_bar_show()
123 dm_pci_read_config32(dev, reg_addr, &size_low); in pci_bar_show()
124 dm_pci_write_config32(dev, reg_addr, base_low); in pci_bar_show()
125 reg_addr += 4; in pci_bar_show()
137 dm_pci_read_config32(dev, reg_addr, &base_high); in pci_bar_show()
138 dm_pci_write_config32(dev, reg_addr, 0xffffffff); in pci_bar_show()
139 dm_pci_read_config32(dev, reg_addr, &size_high); in pci_bar_show()
[all …]
/external/u-boot/drivers/net/phy/
Dcortina.c128 char reg_addr[0x50] = {0}; in cs4340_upload_firmware() local
209 memcpy(reg_addr, line_temp, i); in cs4340_upload_firmware()
211 strim(reg_addr); in cs4340_upload_firmware()
213 fw_temp.reg_addr = (simple_strtoul(reg_addr, NULL, 0)) & 0xffff; in cs4340_upload_firmware()
216 phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value); in cs4340_upload_firmware()
/external/u-boot/arch/arm/mach-sunxi/
Drsb.c144 int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data) in rsb_write() argument
150 writel(reg_addr, &rsb->addr); in rsb_write()
157 int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data) in rsb_read() argument
164 writel(reg_addr, &rsb->addr); in rsb_read()
/external/u-boot/arch/arm/mach-omap2/
Dvc.c94 int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data) in omap_vc_bypass_send_value() argument
104 reg_addr &= PRM_VC_VAL_BYPASS_REGADDR_MASK; in omap_vc_bypass_send_value()
109 reg_addr << PRM_VC_VAL_BYPASS_REGADDR_SHIFT | in omap_vc_bypass_send_value()
/external/u-boot/drivers/ddr/marvell/axp/
Dddr3_init.c789 while (ddr_mode->vals[j].reg_addr != 0) { in ddr3_static_training_init()
791 reg_write(ddr_mode->vals[j].reg_addr, in ddr3_static_training_init()
794 if (ddr_mode->vals[j].reg_addr == in ddr3_static_training_init()
815 u32 ddr3_get_static_mc_value(u32 reg_addr, u32 offset1, u32 mask1, u32 offset2, in ddr3_get_static_mc_value() argument
820 reg = reg_read(reg_addr); in ddr3_get_static_mc_value()
888 while (ddr_mode->regs[j].reg_addr != 0) { in ddr3_static_mc_init()
889 reg_write(ddr_mode->regs[j].reg_addr, in ddr3_static_mc_init()
891 if (ddr_mode->regs[j].reg_addr == in ddr3_static_mc_init()
/external/u-boot/arch/arm/include/asm/arch-sunxi/
Drsb.h51 int rsb_write(const u16 runtime_device_addr, const u8 reg_addr, u8 data);
52 int rsb_read(const u16 runtime_device_addr, const u8 reg_addr, u8 *data);
/external/u-boot/drivers/net/
Dag7xxx.c197 u32 reg_addr; in ag7xxx_switch_reg_read() local
205 reg_addr = 0x10; in ag7xxx_switch_reg_read()
208 reg_addr = 0x00; in ag7xxx_switch_reg_read()
212 ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9); in ag7xxx_switch_reg_read()
237 u32 reg_addr; in ag7xxx_switch_reg_write() local
244 reg_addr = 0x10; in ag7xxx_switch_reg_write()
247 reg_addr = 0x00; in ag7xxx_switch_reg_write()
251 ret = ag7xxx_switch_write(bus, phy_addr, reg_addr, reg >> 9); in ag7xxx_switch_reg_write()
/external/u-boot/arch/arm/mach-omap2/am33xx/
Dboard.c171 static void am33xx_usb_set_phy_power(u8 on, u32 *reg_addr) in am33xx_usb_set_phy_power() argument
174 clrsetbits_le32(reg_addr, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN, in am33xx_usb_set_phy_power()
177 clrsetbits_le32(reg_addr, 0, CM_PHY_PWRDN | CM_PHY_OTG_PWRDN); in am33xx_usb_set_phy_power()
/external/u-boot/include/
Dcortina.h75 unsigned short reg_addr; member
/external/u-boot/arch/arm/include/asm/arch-omap4/
Dsys_proto.h64 int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);

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