Home
last modified time | relevance | path

Searched refs:reg_data (Results 1 – 25 of 26) sorted by relevance

12

/external/u-boot/arch/arm/mach-mvebu/serdes/a38x/
Dseq_exec.c32 u32 unit_base_reg, unit_offset, data, mask, reg_data, reg_addr; in write_op_execute() local
54 reg_data = reg_read(reg_addr); in write_op_execute()
55 reg_data &= (~mask); in write_op_execute()
59 reg_data |= data; in write_op_execute()
60 reg_write(reg_addr, reg_data); in write_op_execute()
63 printf(" - 0x%x\n", reg_data); in write_op_execute()
87 u32 reg_addr, reg_data; in poll_op_execute() local
113 reg_data = reg_read(reg_addr) & mask; in poll_op_execute()
116 } while ((reg_data != data) && (poll_counter < num_of_loops)); in poll_op_execute()
118 if ((poll_counter >= num_of_loops) && (reg_data != data)) { in poll_op_execute()
Dhigh_speed_env_spec.c1564 u32 reg_data; in serdes_pex_usb3_pipe_delay_w_a() local
1568 reg_data = reg_read(GENERAL_PURPOSE_RESERVED0_REG); in serdes_pex_usb3_pipe_delay_w_a()
1578 reg_data |= 1 << (7 + (serdes_num - 3)); in serdes_pex_usb3_pipe_delay_w_a()
1581 reg_data &= ~(1 << (7 + (serdes_num - 3))); in serdes_pex_usb3_pipe_delay_w_a()
1583 reg_write(GENERAL_PURPOSE_RESERVED0_REG, reg_data); in serdes_pex_usb3_pipe_delay_w_a()
1682 u32 reg_data; in serdes_power_up_ctrl() local
1724 reg_data = reg_read(SOC_CONTROL_REG1); in serdes_power_up_ctrl()
1726 reg_data |= 0x4000; in serdes_power_up_ctrl()
1728 reg_data &= ~0x4000; in serdes_power_up_ctrl()
1729 reg_write(SOC_CONTROL_REG1, reg_data); in serdes_power_up_ctrl()
[all …]
/external/u-boot/drivers/phy/marvell/
Dcomphy.h106 u32 reg_data; in reg_set_silent() local
108 reg_data = readl(addr); in reg_set_silent()
109 reg_data &= ~mask; in reg_set_silent()
110 reg_data |= data; in reg_set_silent()
111 writel(reg_data, addr); in reg_set_silent()
125 u16 reg_data; in reg_set_silent16() local
127 reg_data = readw(addr); in reg_set_silent16()
128 reg_data &= ~mask; in reg_set_silent16()
129 reg_data |= data; in reg_set_silent16()
130 writew(reg_data, addr); in reg_set_silent16()
/external/u-boot/drivers/net/pfe_eth/
Dpfe_mdio.c22 u32 reg_data; in pfe_write_addr() local
28 reg_data = (EMAC_MII_DATA_TA | phy | devadr | reg_addr); in pfe_write_addr()
30 writel(reg_data, reg_base + EMAC_MII_DATA_REG); in pfe_write_addr()
56 u32 reg_data; in pfe_phy_read() local
72 reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD | in pfe_phy_read()
75 reg_data = (EMAC_MII_DATA_OP_CL45_RD | EMAC_MII_DATA_TA | in pfe_phy_read()
78 writel(reg_data, reg_base + EMAC_MII_DATA_REG); in pfe_phy_read()
111 u32 reg_data; in pfe_phy_write() local
127 reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR | in pfe_phy_write()
130 reg_data = (EMAC_MII_DATA_OP_CL45_WR | EMAC_MII_DATA_TA | in pfe_phy_write()
[all …]
/external/u-boot/drivers/gpio/
Dbcm6345_gpio.c18 void __iomem *reg_data; member
25 return !!(readl_be(priv->reg_data) & BIT(offset)); in bcm6345_gpio_get_value()
34 setbits_be32(priv->reg_data, BIT(offset)); in bcm6345_gpio_set_value()
36 clrbits_be32(priv->reg_data, BIT(offset)); in bcm6345_gpio_set_value()
96 priv->reg_data = dev_remap_addr_index(dev, 1); in bcm6345_gpio_probe()
97 if (!priv->reg_data) in bcm6345_gpio_probe()
/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_debug.c529 u32 reg_data; in ddr3_tip_print_stability_log() local
587 csindex, &reg_data); in ddr3_tip_print_stability_log()
588 printf("%d,%d,", (reg_data & 0x1f), in ddr3_tip_print_stability_log()
589 ((reg_data & 0x3e0) >> 5)); in ddr3_tip_print_stability_log()
595 &reg_data); in ddr3_tip_print_stability_log()
597 (reg_data & 0x1f) + in ddr3_tip_print_stability_log()
598 ((reg_data & 0x1c0) >> 6) * 32, in ddr3_tip_print_stability_log()
599 (reg_data & 0x1f), in ddr3_tip_print_stability_log()
600 (reg_data & 0x1c0) >> 6); in ddr3_tip_print_stability_log()
615 &reg_data); in ddr3_tip_print_stability_log()
[all …]
Dddr3_training_ip_engine.c347 reg_data, pup_id; in ddr3_tip_ip_training() local
409 reg_data = (direction == OPER_READ) ? 0 : (0x3 << 30); in ddr3_tip_ip_training()
410 reg_data |= (direction == OPER_READ) ? 0x60 : 0xfa; in ddr3_tip_ip_training()
413 ODPG_WR_RD_MODE_ENA_REG, reg_data, in ddr3_tip_ip_training()
415 reg_data = (edge_comp == EDGE_PF || edge_comp == EDGE_FP) ? 0 : 1 << 6; in ddr3_tip_ip_training()
416 reg_data |= (edge_comp == EDGE_PF || edge_comp == EDGE_PFP) ? in ddr3_tip_ip_training()
421 reg_data |= 0xe << 14; in ddr3_tip_ip_training()
423 reg_data |= pup_num << 14; in ddr3_tip_ip_training()
427 reg_data |= (0 << 20); in ddr3_tip_ip_training()
429 reg_data |= (0 << 20); in ddr3_tip_ip_training()
[all …]
Dddr3_training_leveling.c833 u32 reg_data = 0, temp = 0, iter, if_id, bus_cnt; in ddr3_tip_dynamic_write_leveling() local
943 reg_data = data_read[0]; in ddr3_tip_dynamic_write_leveling()
946 reg_data = 0; in ddr3_tip_dynamic_write_leveling()
948 if (reg_data != PASS) in ddr3_tip_dynamic_write_leveling()
958 reg_data = data_read[0]; in ddr3_tip_dynamic_write_leveling()
960 0, bus_cnt, reg_data)); in ddr3_tip_dynamic_write_leveling()
961 if ((reg_data & (1 << 25)) == 0) in ddr3_tip_dynamic_write_leveling()
985 reg_data = wl_values[effective_cs][bus_cnt][if_id] + 16; in ddr3_tip_dynamic_write_leveling()
990 reg_data = (reg_data & 0x1f) | in ddr3_tip_dynamic_write_leveling()
991 (((reg_data & 0xe0) >> 5) << 6) | in ddr3_tip_dynamic_write_leveling()
[all …]
Dddr3_training_ip_def.h185 struct reg_data { struct
187 unsigned int reg_data; argument
Dddr3_training_hw_algo.c114 u32 reg_data; in get_valid_win_rx() local
127 &reg_data)); in get_valid_win_rx()
128 res[i] = (reg_data >> RESULT_PHY_RX_OFFS) & 0x1f; in get_valid_win_rx()
Dmv_ddr_plat.h212 u32 reg_data; member
Dmv_ddr_plat.c1299 config_table_ptr[i].reg_data); in ddr3_new_tip_dlb_config()
/external/u-boot/arch/arm/mach-omap2/
Dvc.c94 int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data) in omap_vc_bypass_send_value() argument
105 reg_data &= PRM_VC_VAL_BYPASS_DATA_MASK; in omap_vc_bypass_send_value()
110 reg_data << PRM_VC_VAL_BYPASS_DATA_SHIFT; in omap_vc_bypass_send_value()
/external/u-boot/drivers/net/
De1000.c1351 uint32_t reg_data = 0; in e1000_read_mac_addr_from_regs() local
1361 reg_data = E1000_READ_REG_ARRAY(hw, RA, 0); in e1000_read_mac_addr_from_regs()
1363 reg_data >>= 16; in e1000_read_mac_addr_from_regs()
1365 reg_data = E1000_READ_REG_ARRAY(hw, RA, 1); in e1000_read_mac_addr_from_regs()
1366 tmp = reg_data & 0xffff; in e1000_read_mac_addr_from_regs()
1852 uint32_t reg_data; in e1000_init_hw() local
1860 reg_data = E1000_READ_REG(hw, STATUS); in e1000_init_hw()
1861 reg_data &= ~0x80000000; in e1000_init_hw()
1862 E1000_WRITE_REG(hw, STATUS, reg_data); in e1000_init_hw()
2002 reg_data = E1000_READ_REG(hw, TCTL); in e1000_init_hw()
[all …]
Dks8851_mll.c189 u16 reg_data = 0; in ks_read_config() local
192 reg_data = ks_rdreg8(dev, KS_CCR) & 0x00FF; in ks_read_config()
193 reg_data |= ks_rdreg8(dev, KS_CCR + 1) << 8; in ks_read_config()
196 ks->sharedbus = (reg_data & CCR_SHARED) == CCR_SHARED; in ks_read_config()
202 if (reg_data & CCR_8BIT) { in ks_read_config()
205 } else if (reg_data & CCR_16BIT) { in ks_read_config()
Dmvgbe.c179 u32 reg_data; in stop_queue() local
181 reg_data = readl(qreg); in stop_queue()
183 if (reg_data & 0xFF) { in stop_queue()
185 writel((reg_data << 8), qreg); in stop_queue()
193 reg_data = readl(qreg); in stop_queue()
195 while (reg_data & 0xFF); in stop_queue()
Dmvpp2.c3819 u32 reg_data; in mvpp2_egress_disable() local
3825 reg_data = (mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG)) & in mvpp2_egress_disable()
3827 if (reg_data != 0) in mvpp2_egress_disable()
3829 (reg_data << MVPP2_TXP_SCHED_DISQ_OFFSET)); in mvpp2_egress_disable()
3837 reg_data); in mvpp2_egress_disable()
3846 reg_data = mvpp2_read(port->priv, MVPP2_TXP_SCHED_Q_CMD_REG); in mvpp2_egress_disable()
3847 } while (reg_data & MVPP2_TXP_SCHED_ENQ_MASK); in mvpp2_egress_disable()
/external/u-boot/drivers/sound/
Dwm8994.c296 unsigned short reg_data; in wm8994_hw_params() local
389 if (wm8994_i2c_read(aif1_reg, &reg_data) != 0) { in wm8994_hw_params()
394 if ((channels == 1) && ((reg_data & 0x18) == 0x18)) in wm8994_hw_params()
657 unsigned short reg_data; in wm8994_device_init() local
662 ret = wm8994_i2c_read(WM8994_SOFTWARE_RESET, &reg_data); in wm8994_device_init()
668 if (reg_data == WM8994_ID) { in wm8994_device_init()
678 ret = wm8994_i2c_read(WM8994_CHIP_REVISION, &reg_data); in wm8994_device_init()
683 wm8994->revision = reg_data; in wm8994_device_init()
/external/u-boot/drivers/net/phy/
Dcortina.c129 char reg_data[0x50] = {0}; in cs4340_upload_firmware() local
210 memcpy(reg_data, &line_temp[i], column_cnt - i); in cs4340_upload_firmware()
212 strim(reg_data); in cs4340_upload_firmware()
214 fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) & in cs4340_upload_firmware()
/external/u-boot/arch/arm/include/asm/arch-omap4/
Dsys_proto.h64 int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
/external/u-boot/arch/arm/include/asm/arch-omap5/
Dsys_proto.h71 int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data);
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
D2009-07-15-CoalescerBug.ll22 … { i32*, i32*, %struct.regnode*, %struct.reg_substr_data*, i8*, %struct.reg_data*, i8*, i32*, i32,…
33 %struct.reg_data = type { i32, i8*, [1 x i8*] }
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
D2009-07-15-CoalescerBug.ll22 … { i32*, i32*, %struct.regnode*, %struct.reg_substr_data*, i8*, %struct.reg_data*, i8*, i32*, i32,…
33 %struct.reg_data = type { i32, i8*, [1 x i8*] }
/external/llvm/test/CodeGen/X86/
D2009-07-15-CoalescerBug.ll22 … { i32*, i32*, %struct.regnode*, %struct.reg_substr_data*, i8*, %struct.reg_data*, i8*, i32*, i32,…
33 %struct.reg_data = type { i32, i8*, [1 x i8*] }
/external/u-boot/arch/arm/include/asm/
Domap_common.h540 int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data);

12