| /external/u-boot/arch/arm/mach-socfpga/ |
| D | freeze_controller.c | 28 u32 reg_value; in sys_mgr_frzctrl_freeze_req() local
80 reg_value = readl(&freeze_controller_base->hioctrl); in sys_mgr_frzctrl_freeze_req()
84 reg_value in sys_mgr_frzctrl_freeze_req()
85 = (reg_value & ~reg_cfg_mask) in sys_mgr_frzctrl_freeze_req()
88 writel(reg_value, &freeze_controller_base->hioctrl); in sys_mgr_frzctrl_freeze_req()
94 reg_value = readl(&freeze_controller_base->hioctrl); in sys_mgr_frzctrl_freeze_req()
95 reg_value in sys_mgr_frzctrl_freeze_req()
96 = (reg_value & in sys_mgr_frzctrl_freeze_req()
99 writel(reg_value, &freeze_controller_base->hioctrl); in sys_mgr_frzctrl_freeze_req()
110 u32 reg_value; in sys_mgr_frzctrl_thaw_req() local
[all …]
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| /external/u-boot/drivers/ram/rockchip/ |
| D | sdram_rk3399.c | 164 u32 reg_value; in set_ds_odt() local
211 reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) | in set_ds_odt()
214 clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value); in set_ds_odt()
215 clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value); in set_ds_odt()
216 clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value); in set_ds_odt()
217 clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value); in set_ds_odt()
224 clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value); in set_ds_odt()
225 clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value); in set_ds_odt()
226 clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value); in set_ds_odt()
227 clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value); in set_ds_odt()
[all …]
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| /external/u-boot/drivers/net/phy/ |
| D | cortina.c | 214 fw_temp.reg_value = (simple_strtoul(reg_data, NULL, 0)) & in cs4340_upload_firmware()
216 phy_write(phydev, 0x00, fw_temp.reg_addr, fw_temp.reg_value); in cs4340_upload_firmware()
226 int reg_value; in cs4340_phy_init() local
240 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_BIST_STATUS); in cs4340_phy_init()
241 if (reg_value & mseq_edc_bist_done) { in cs4340_phy_init()
242 if (0 == (reg_value & mseq_edc_bist_fail)) in cs4340_phy_init()
256 reg_value = phy_read(phydev, 0x00, VILLA_GLOBAL_DWNLD_CHECKSUM_STATUS); in cs4340_phy_init()
257 if (reg_value) { in cs4340_phy_init()
289 int reg_value; in cs4223_phy_init() local
291 reg_value = phy_read(phydev, 0x00, CS4223_EEPROM_STATUS); in cs4223_phy_init()
[all …]
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| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| D | radeon_pair_schedule.c | 51 struct reg_value * WriteValues[4];
52 struct reg_value * ReadValues[12];
97 struct reg_value { struct
115 struct reg_value *Next; /**< Pointer to the next value to be written to the same register */ argument
119 struct reg_value * Values[4];
160 static struct reg_value ** get_reg_valuep(struct schedule_state * s, in get_reg_valuep()
286 struct reg_value * v = sinst->WriteValues[i];
372 struct reg_value * v = sinst->ReadValues[i]; in commit_update_reads()
390 struct reg_value * v = sinst->WriteValues[i]; in commit_update_writes()
914 struct reg_value ** new_regvalp = get_reg_valuep( in convert_rgb_to_alpha()
[all …]
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| /external/u-boot/drivers/usb/musb-new/ |
| D | sunxi.c | 171 u32 reg_value; in USBC_ConfigFIFO_Base() local
174 reg_value = readl(SUNXI_SRAMC_BASE + 0x04); in USBC_ConfigFIFO_Base()
175 reg_value &= ~(0x03 << 0); in USBC_ConfigFIFO_Base()
176 reg_value |= BIT(0); in USBC_ConfigFIFO_Base()
177 writel(reg_value, SUNXI_SRAMC_BASE + 0x04); in USBC_ConfigFIFO_Base()
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| /external/u-boot/drivers/video/sunxi/ |
| D | sunxi_de2.c | 39 u32 reg_value; in sunxi_de2_composer_init() local
42 reg_value = readl(SUNXI_SRAMC_BASE + 0x04); in sunxi_de2_composer_init()
43 reg_value &= ~(0x01 << 24); in sunxi_de2_composer_init()
44 writel(reg_value, SUNXI_SRAMC_BASE + 0x04); in sunxi_de2_composer_init()
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| /external/u-boot/drivers/phy/allwinner/ |
| D | phy-sun4i-usb.c | 194 u32 bits, reg_value; in sun4i_usb_phy_passby() local
207 reg_value = readl(usb_phy->pmu); in sun4i_usb_phy_passby()
210 reg_value |= bits; in sun4i_usb_phy_passby()
212 reg_value &= ~bits; in sun4i_usb_phy_passby()
214 writel(reg_value, usb_phy->pmu); in sun4i_usb_phy_passby()
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| /external/u-boot/include/ |
| D | cortina.h | 76 unsigned short reg_value; member
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| /external/u-boot/drivers/ddr/marvell/axp/ |
| D | ddr3_hw_training.h | 288 u32 reg_value; member
293 u32 reg_value; member
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| D | ddr3_init.c | 792 ddr_mode->vals[j].reg_value); in ddr3_static_training_init()
890 ddr_mode->regs[j].reg_value); in ddr3_static_mc_init()
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| /external/v8/src/compiler/ppc/ |
| D | code-generator-ppc.cc | 2217 int reg_value = -1; in AssembleArchBoolean() local
2228 reg_value = 0; in AssembleArchBoolean()
2232 reg_value = 1; in AssembleArchBoolean()
2244 if (reg_value != 1) __ li(reg, Operand(1)); in AssembleArchBoolean()
2251 if (reg_value != 1) __ li(reg, Operand(1)); in AssembleArchBoolean()
2260 if (reg_value != 0) __ li(reg, Operand::Zero()); in AssembleArchBoolean()
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